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PCNT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x5C0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

U0_CONF0

U1_CONF1

U1_CONF2

U2_CONF0

U2_CONF1

U2_CONF2

U3_CONF0

U3_CONF1

U3_CONF2

U4_CONF0

U4_CONF1

U4_CONF2

U5_CONF0

U0_CONF1

U5_CONF1

U5_CONF2

U6_CONF0

U6_CONF1

U6_CONF2

U7_CONF0

U7_CONF1

U7_CONF2

U0_CNT

U1_CNT

U2_CNT

U3_CNT

U4_CNT

U5_CNT

U6_CNT

U7_CNT

U0_CONF2

INT_RAW

INT_ST

INT_ENA

INT_CLR

U0_STATUS

U1_STATUS

U2_STATUS

U3_STATUS

U4_STATUS

U5_STATUS

U6_STATUS

U7_STATUS

CTRL

U1_CONF0

DATE


U0_CONF0

PCNT_U0_CONF0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0_CONF0 U0_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U0 FILTER_EN_U0 THR_ZERO_EN_U0 THR_H_LIM_EN_U0 THR_L_LIM_EN_U0 THR_THRES0_EN_U0 THR_THRES1_EN_U0 CH0_NEG_MODE_U0 CH0_POS_MODE_U0 CH0_HCTRL_MODE_U0 CH0_LCTRL_MODE_U0 CH1_NEG_MODE_U0 CH1_POS_MODE_U0 CH1_HCTRL_MODE_U0 CH1_LCTRL_MODE_U0

FILTER_THRES_U0 :
bits : 0 - 9 (10 bit)

FILTER_EN_U0 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U0 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U0 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U0 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U0 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U0 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U0 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U0 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U0 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U0 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U0 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U0 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U0 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U0 :
bits : 30 - 31 (2 bit)


U1_CONF1

PCNT_U1_CONF1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U1_CONF1 U1_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U1 CNT_THRES1_U1

CNT_THRES0_U1 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U1 :
bits : 16 - 31 (16 bit)


U1_CONF2

PCNT_U1_CONF2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U1_CONF2 U1_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U1 CNT_L_LIM_U1

CNT_H_LIM_U1 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U1 :
bits : 16 - 31 (16 bit)


U2_CONF0

PCNT_U2_CONF0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U2_CONF0 U2_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U2 FILTER_EN_U2 THR_ZERO_EN_U2 THR_H_LIM_EN_U2 THR_L_LIM_EN_U2 THR_THRES0_EN_U2 THR_THRES1_EN_U2 CH0_NEG_MODE_U2 CH0_POS_MODE_U2 CH0_HCTRL_MODE_U2 CH0_LCTRL_MODE_U2 CH1_NEG_MODE_U2 CH1_POS_MODE_U2 CH1_HCTRL_MODE_U2 CH1_LCTRL_MODE_U2

FILTER_THRES_U2 :
bits : 0 - 9 (10 bit)

FILTER_EN_U2 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U2 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U2 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U2 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U2 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U2 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U2 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U2 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U2 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U2 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U2 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U2 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U2 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U2 :
bits : 30 - 31 (2 bit)


U2_CONF1

PCNT_U2_CONF1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U2_CONF1 U2_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U2 CNT_THRES1_U2

CNT_THRES0_U2 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U2 :
bits : 16 - 31 (16 bit)


U2_CONF2

PCNT_U2_CONF2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U2_CONF2 U2_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U2 CNT_L_LIM_U2

CNT_H_LIM_U2 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U2 :
bits : 16 - 31 (16 bit)


U3_CONF0

PCNT_U3_CONF0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U3_CONF0 U3_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U3 FILTER_EN_U3 THR_ZERO_EN_U3 THR_H_LIM_EN_U3 THR_L_LIM_EN_U3 THR_THRES0_EN_U3 THR_THRES1_EN_U3 CH0_NEG_MODE_U3 CH0_POS_MODE_U3 CH0_HCTRL_MODE_U3 CH0_LCTRL_MODE_U3 CH1_NEG_MODE_U3 CH1_POS_MODE_U3 CH1_HCTRL_MODE_U3 CH1_LCTRL_MODE_U3

FILTER_THRES_U3 :
bits : 0 - 9 (10 bit)

FILTER_EN_U3 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U3 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U3 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U3 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U3 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U3 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U3 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U3 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U3 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U3 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U3 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U3 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U3 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U3 :
bits : 30 - 31 (2 bit)


U3_CONF1

PCNT_U3_CONF1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U3_CONF1 U3_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U3 CNT_THRES1_U3

CNT_THRES0_U3 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U3 :
bits : 16 - 31 (16 bit)


U3_CONF2

PCNT_U3_CONF2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U3_CONF2 U3_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U3 CNT_L_LIM_U3

CNT_H_LIM_U3 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U3 :
bits : 16 - 31 (16 bit)


U4_CONF0

PCNT_U4_CONF0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U4_CONF0 U4_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U4 FILTER_EN_U4 THR_ZERO_EN_U4 THR_H_LIM_EN_U4 THR_L_LIM_EN_U4 THR_THRES0_EN_U4 THR_THRES1_EN_U4 CH0_NEG_MODE_U4 CH0_POS_MODE_U4 CH0_HCTRL_MODE_U4 CH0_LCTRL_MODE_U4 CH1_NEG_MODE_U4 CH1_POS_MODE_U4 CH1_HCTRL_MODE_U4 CH1_LCTRL_MODE_U4

FILTER_THRES_U4 :
bits : 0 - 9 (10 bit)

FILTER_EN_U4 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U4 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U4 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U4 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U4 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U4 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U4 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U4 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U4 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U4 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U4 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U4 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U4 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U4 :
bits : 30 - 31 (2 bit)


U4_CONF1

PCNT_U4_CONF1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U4_CONF1 U4_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U4 CNT_THRES1_U4

CNT_THRES0_U4 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U4 :
bits : 16 - 31 (16 bit)


U4_CONF2

PCNT_U4_CONF2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U4_CONF2 U4_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U4 CNT_L_LIM_U4

CNT_H_LIM_U4 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U4 :
bits : 16 - 31 (16 bit)


U5_CONF0

PCNT_U5_CONF0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U5_CONF0 U5_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U5 FILTER_EN_U5 THR_ZERO_EN_U5 THR_H_LIM_EN_U5 THR_L_LIM_EN_U5 THR_THRES0_EN_U5 THR_THRES1_EN_U5 CH0_NEG_MODE_U5 CH0_POS_MODE_U5 CH0_HCTRL_MODE_U5 CH0_LCTRL_MODE_U5 CH1_NEG_MODE_U5 CH1_POS_MODE_U5 CH1_HCTRL_MODE_U5 CH1_LCTRL_MODE_U5

FILTER_THRES_U5 :
bits : 0 - 9 (10 bit)

FILTER_EN_U5 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U5 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U5 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U5 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U5 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U5 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U5 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U5 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U5 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U5 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U5 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U5 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U5 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U5 :
bits : 30 - 31 (2 bit)


U0_CONF1

PCNT_U0_CONF1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0_CONF1 U0_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U0 CNT_THRES1_U0

CNT_THRES0_U0 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U0 :
bits : 16 - 31 (16 bit)


U5_CONF1

PCNT_U5_CONF1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U5_CONF1 U5_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U5 CNT_THRES1_U5

CNT_THRES0_U5 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U5 :
bits : 16 - 31 (16 bit)


U5_CONF2

PCNT_U5_CONF2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U5_CONF2 U5_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U5 CNT_L_LIM_U5

CNT_H_LIM_U5 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U5 :
bits : 16 - 31 (16 bit)


U6_CONF0

PCNT_U6_CONF0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U6_CONF0 U6_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U6 FILTER_EN_U6 THR_ZERO_EN_U6 THR_H_LIM_EN_U6 THR_L_LIM_EN_U6 THR_THRES0_EN_U6 THR_THRES1_EN_U6 CH0_NEG_MODE_U6 CH0_POS_MODE_U6 CH0_HCTRL_MODE_U6 CH0_LCTRL_MODE_U6 CH1_NEG_MODE_U6 CH1_POS_MODE_U6 CH1_HCTRL_MODE_U6 CH1_LCTRL_MODE_U6

FILTER_THRES_U6 :
bits : 0 - 9 (10 bit)

FILTER_EN_U6 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U6 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U6 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U6 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U6 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U6 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U6 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U6 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U6 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U6 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U6 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U6 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U6 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U6 :
bits : 30 - 31 (2 bit)


U6_CONF1

PCNT_U6_CONF1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U6_CONF1 U6_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U6 CNT_THRES1_U6

CNT_THRES0_U6 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U6 :
bits : 16 - 31 (16 bit)


U6_CONF2

PCNT_U6_CONF2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U6_CONF2 U6_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U6 CNT_L_LIM_U6

CNT_H_LIM_U6 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U6 :
bits : 16 - 31 (16 bit)


U7_CONF0

PCNT_U7_CONF0
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U7_CONF0 U7_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U7 FILTER_EN_U7 THR_ZERO_EN_U7 THR_H_LIM_EN_U7 THR_L_LIM_EN_U7 THR_THRES0_EN_U7 THR_THRES1_EN_U7 CH0_NEG_MODE_U7 CH0_POS_MODE_U7 CH0_HCTRL_MODE_U7 CH0_LCTRL_MODE_U7 CH1_NEG_MODE_U7 CH1_POS_MODE_U7 CH1_HCTRL_MODE_U7 CH1_LCTRL_MODE_U7

FILTER_THRES_U7 :
bits : 0 - 9 (10 bit)

FILTER_EN_U7 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U7 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U7 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U7 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U7 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U7 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U7 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U7 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U7 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U7 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U7 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U7 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U7 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U7 :
bits : 30 - 31 (2 bit)


U7_CONF1

PCNT_U7_CONF1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U7_CONF1 U7_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THRES0_U7 CNT_THRES1_U7

CNT_THRES0_U7 :
bits : 0 - 15 (16 bit)

CNT_THRES1_U7 :
bits : 16 - 31 (16 bit)


U7_CONF2

PCNT_U7_CONF2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U7_CONF2 U7_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U7 CNT_L_LIM_U7

CNT_H_LIM_U7 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U7 :
bits : 16 - 31 (16 bit)


U0_CNT

PCNT_U0_CNT
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0_CNT U0_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U0

PLUS_CNT_U0 :
bits : 0 - 15 (16 bit)


U1_CNT

PCNT_U1_CNT
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U1_CNT U1_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U1

PLUS_CNT_U1 :
bits : 0 - 15 (16 bit)


U2_CNT

PCNT_U2_CNT
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U2_CNT U2_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U2

PLUS_CNT_U2 :
bits : 0 - 15 (16 bit)


U3_CNT

PCNT_U3_CNT
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U3_CNT U3_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U3

PLUS_CNT_U3 :
bits : 0 - 15 (16 bit)


U4_CNT

PCNT_U4_CNT
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U4_CNT U4_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U4

PLUS_CNT_U4 :
bits : 0 - 15 (16 bit)


U5_CNT

PCNT_U5_CNT
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U5_CNT U5_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U5

PLUS_CNT_U5 :
bits : 0 - 15 (16 bit)


U6_CNT

PCNT_U6_CNT
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U6_CNT U6_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U6

PLUS_CNT_U6 :
bits : 0 - 15 (16 bit)


U7_CNT

PCNT_U7_CNT
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U7_CNT U7_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_U7

PLUS_CNT_U7 :
bits : 0 - 15 (16 bit)


U0_CONF2

PCNT_U0_CONF2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0_CONF2 U0_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_H_LIM_U0 CNT_L_LIM_U0

CNT_H_LIM_U0 :
bits : 0 - 15 (16 bit)

CNT_L_LIM_U0 :
bits : 16 - 31 (16 bit)


INT_RAW

PCNT_INT_RAW
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THR_EVENT_U0_INT_RAW CNT_THR_EVENT_U1_INT_RAW CNT_THR_EVENT_U2_INT_RAW CNT_THR_EVENT_U3_INT_RAW CNT_THR_EVENT_U4_INT_RAW CNT_THR_EVENT_U5_INT_RAW CNT_THR_EVENT_U6_INT_RAW CNT_THR_EVENT_U7_INT_RAW

CNT_THR_EVENT_U0_INT_RAW :
bits : 0 - 0 (1 bit)

CNT_THR_EVENT_U1_INT_RAW :
bits : 1 - 1 (1 bit)

CNT_THR_EVENT_U2_INT_RAW :
bits : 2 - 2 (1 bit)

CNT_THR_EVENT_U3_INT_RAW :
bits : 3 - 3 (1 bit)

CNT_THR_EVENT_U4_INT_RAW :
bits : 4 - 4 (1 bit)

CNT_THR_EVENT_U5_INT_RAW :
bits : 5 - 5 (1 bit)

CNT_THR_EVENT_U6_INT_RAW :
bits : 6 - 6 (1 bit)

CNT_THR_EVENT_U7_INT_RAW :
bits : 7 - 7 (1 bit)


INT_ST

PCNT_INT_ST
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ST INT_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THR_EVENT_U0_INT_ST CNT_THR_EVENT_U1_INT_ST CNT_THR_EVENT_U2_INT_ST CNT_THR_EVENT_U3_INT_ST CNT_THR_EVENT_U4_INT_ST CNT_THR_EVENT_U5_INT_ST CNT_THR_EVENT_U6_INT_ST CNT_THR_EVENT_U7_INT_ST

CNT_THR_EVENT_U0_INT_ST :
bits : 0 - 0 (1 bit)

CNT_THR_EVENT_U1_INT_ST :
bits : 1 - 1 (1 bit)

CNT_THR_EVENT_U2_INT_ST :
bits : 2 - 2 (1 bit)

CNT_THR_EVENT_U3_INT_ST :
bits : 3 - 3 (1 bit)

CNT_THR_EVENT_U4_INT_ST :
bits : 4 - 4 (1 bit)

CNT_THR_EVENT_U5_INT_ST :
bits : 5 - 5 (1 bit)

CNT_THR_EVENT_U6_INT_ST :
bits : 6 - 6 (1 bit)

CNT_THR_EVENT_U7_INT_ST :
bits : 7 - 7 (1 bit)


INT_ENA

PCNT_INT_ENA
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THR_EVENT_U0_INT_ENA CNT_THR_EVENT_U1_INT_ENA CNT_THR_EVENT_U2_INT_ENA CNT_THR_EVENT_U3_INT_ENA CNT_THR_EVENT_U4_INT_ENA CNT_THR_EVENT_U5_INT_ENA CNT_THR_EVENT_U6_INT_ENA CNT_THR_EVENT_U7_INT_ENA

CNT_THR_EVENT_U0_INT_ENA :
bits : 0 - 0 (1 bit)

CNT_THR_EVENT_U1_INT_ENA :
bits : 1 - 1 (1 bit)

CNT_THR_EVENT_U2_INT_ENA :
bits : 2 - 2 (1 bit)

CNT_THR_EVENT_U3_INT_ENA :
bits : 3 - 3 (1 bit)

CNT_THR_EVENT_U4_INT_ENA :
bits : 4 - 4 (1 bit)

CNT_THR_EVENT_U5_INT_ENA :
bits : 5 - 5 (1 bit)

CNT_THR_EVENT_U6_INT_ENA :
bits : 6 - 6 (1 bit)

CNT_THR_EVENT_U7_INT_ENA :
bits : 7 - 7 (1 bit)


INT_CLR

PCNT_INT_CLR
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT_THR_EVENT_U0_INT_CLR CNT_THR_EVENT_U1_INT_CLR CNT_THR_EVENT_U2_INT_CLR CNT_THR_EVENT_U3_INT_CLR CNT_THR_EVENT_U4_INT_CLR CNT_THR_EVENT_U5_INT_CLR CNT_THR_EVENT_U6_INT_CLR CNT_THR_EVENT_U7_INT_CLR

CNT_THR_EVENT_U0_INT_CLR :
bits : 0 - 0 (1 bit)

CNT_THR_EVENT_U1_INT_CLR :
bits : 1 - 1 (1 bit)

CNT_THR_EVENT_U2_INT_CLR :
bits : 2 - 2 (1 bit)

CNT_THR_EVENT_U3_INT_CLR :
bits : 3 - 3 (1 bit)

CNT_THR_EVENT_U4_INT_CLR :
bits : 4 - 4 (1 bit)

CNT_THR_EVENT_U5_INT_CLR :
bits : 5 - 5 (1 bit)

CNT_THR_EVENT_U6_INT_CLR :
bits : 6 - 6 (1 bit)

CNT_THR_EVENT_U7_INT_CLR :
bits : 7 - 7 (1 bit)


U0_STATUS

PCNT_U0_STATUS
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0_STATUS U0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U0

CORE_STATUS_U0 :
bits : 0 - 31 (32 bit)


U1_STATUS

PCNT_U1_STATUS
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U1_STATUS U1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U1

CORE_STATUS_U1 :
bits : 0 - 31 (32 bit)


U2_STATUS

PCNT_U2_STATUS
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U2_STATUS U2_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U2

CORE_STATUS_U2 :
bits : 0 - 31 (32 bit)


U3_STATUS

PCNT_U3_STATUS
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U3_STATUS U3_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U3

CORE_STATUS_U3 :
bits : 0 - 31 (32 bit)


U4_STATUS

PCNT_U4_STATUS
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U4_STATUS U4_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U4

CORE_STATUS_U4 :
bits : 0 - 31 (32 bit)


U5_STATUS

PCNT_U5_STATUS
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U5_STATUS U5_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U5

CORE_STATUS_U5 :
bits : 0 - 31 (32 bit)


U6_STATUS

PCNT_U6_STATUS
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U6_STATUS U6_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U6

CORE_STATUS_U6 :
bits : 0 - 31 (32 bit)


U7_STATUS

PCNT_U7_STATUS
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U7_STATUS U7_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_STATUS_U7

CORE_STATUS_U7 :
bits : 0 - 31 (32 bit)


CTRL

PCNT_CTRL
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLUS_CNT_RST_U0 CNT_PAUSE_U0 PLUS_CNT_RST_U1 CNT_PAUSE_U1 PLUS_CNT_RST_U2 CNT_PAUSE_U2 PLUS_CNT_RST_U3 CNT_PAUSE_U3 PLUS_CNT_RST_U4 CNT_PAUSE_U4 PLUS_CNT_RST_U5 CNT_PAUSE_U5 PLUS_CNT_RST_U6 CNT_PAUSE_U6 PLUS_CNT_RST_U7 CNT_PAUSE_U7 CLK_EN

PLUS_CNT_RST_U0 :
bits : 0 - 0 (1 bit)

CNT_PAUSE_U0 :
bits : 1 - 1 (1 bit)

PLUS_CNT_RST_U1 :
bits : 2 - 2 (1 bit)

CNT_PAUSE_U1 :
bits : 3 - 3 (1 bit)

PLUS_CNT_RST_U2 :
bits : 4 - 4 (1 bit)

CNT_PAUSE_U2 :
bits : 5 - 5 (1 bit)

PLUS_CNT_RST_U3 :
bits : 6 - 6 (1 bit)

CNT_PAUSE_U3 :
bits : 7 - 7 (1 bit)

PLUS_CNT_RST_U4 :
bits : 8 - 8 (1 bit)

CNT_PAUSE_U4 :
bits : 9 - 9 (1 bit)

PLUS_CNT_RST_U5 :
bits : 10 - 10 (1 bit)

CNT_PAUSE_U5 :
bits : 11 - 11 (1 bit)

PLUS_CNT_RST_U6 :
bits : 12 - 12 (1 bit)

CNT_PAUSE_U6 :
bits : 13 - 13 (1 bit)

PLUS_CNT_RST_U7 :
bits : 14 - 14 (1 bit)

CNT_PAUSE_U7 :
bits : 15 - 15 (1 bit)

CLK_EN :
bits : 16 - 16 (1 bit)


U1_CONF0

PCNT_U1_CONF0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U1_CONF0 U1_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_THRES_U1 FILTER_EN_U1 THR_ZERO_EN_U1 THR_H_LIM_EN_U1 THR_L_LIM_EN_U1 THR_THRES0_EN_U1 THR_THRES1_EN_U1 CH0_NEG_MODE_U1 CH0_POS_MODE_U1 CH0_HCTRL_MODE_U1 CH0_LCTRL_MODE_U1 CH1_NEG_MODE_U1 CH1_POS_MODE_U1 CH1_HCTRL_MODE_U1 CH1_LCTRL_MODE_U1

FILTER_THRES_U1 :
bits : 0 - 9 (10 bit)

FILTER_EN_U1 :
bits : 10 - 10 (1 bit)

THR_ZERO_EN_U1 :
bits : 11 - 11 (1 bit)

THR_H_LIM_EN_U1 :
bits : 12 - 12 (1 bit)

THR_L_LIM_EN_U1 :
bits : 13 - 13 (1 bit)

THR_THRES0_EN_U1 :
bits : 14 - 14 (1 bit)

THR_THRES1_EN_U1 :
bits : 15 - 15 (1 bit)

CH0_NEG_MODE_U1 :
bits : 16 - 17 (2 bit)

CH0_POS_MODE_U1 :
bits : 18 - 19 (2 bit)

CH0_HCTRL_MODE_U1 :
bits : 20 - 21 (2 bit)

CH0_LCTRL_MODE_U1 :
bits : 22 - 23 (2 bit)

CH1_NEG_MODE_U1 :
bits : 24 - 25 (2 bit)

CH1_POS_MODE_U1 :
bits : 26 - 27 (2 bit)

CH1_HCTRL_MODE_U1 :
bits : 28 - 29 (2 bit)

CH1_LCTRL_MODE_U1 :
bits : 30 - 31 (2 bit)


DATE

PCNT_DATE
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 31 (32 bit)



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