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RMT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x6C0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CH0CONF0

CH0CONF1

CH1CONF0

CH1CONF1

CH2CONF0

CH2CONF1

CH3CONF0

CH3CONF1

CH4CONF0

CH4CONF1

CH5CONF0

CH5CONF1

CH6CONF0

CH6CONF1

CH7CONF0

CH7CONF1

CH0STATUS

CH1STATUS

CH2STATUS

CH3STATUS

CH4STATUS

CH5STATUS

CH6STATUS

CH7STATUS

CH0ADDR

CH1ADDR

CH2ADDR

CH3ADDR

CH4ADDR

CH5ADDR

CH6ADDR

CH7ADDR

INT_RAW

INT_ST

INT_ENA

INT_CLR

CH0CARRIER_DUTY

CH1CARRIER_DUTY

CH2CARRIER_DUTY

CH3CARRIER_DUTY

CH4CARRIER_DUTY

CH5CARRIER_DUTY

CH6CARRIER_DUTY

CH7CARRIER_DUTY

CH0_TX_LIM

CH1_TX_LIM

CH2_TX_LIM

CH3_TX_LIM

CH4_TX_LIM

CH5_TX_LIM

CH6_TX_LIM

CH7_TX_LIM

APB_CONF

DATE


CH0CONF0

RMT_CH0CONF0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CONF0 CH0CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH0 IDLE_THRES_CH0 MEM_SIZE_CH0 CARRIER_EN_CH0 CARRIER_OUT_LV_CH0 MEM_PD CLK_EN

DIV_CNT_CH0 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH0 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH0 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH0 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH0 :
bits : 29 - 29 (1 bit)

MEM_PD :
bits : 30 - 30 (1 bit)

CLK_EN :
bits : 31 - 31 (1 bit)


CH0CONF1

RMT_CH0CONF1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CONF1 CH0CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH0 RX_EN_CH0 MEM_WR_RST_CH0 MEM_RD_RST_CH0 APB_MEM_RST_CH0 MEM_OWNER_CH0 TX_CONTI_MODE_CH0 RX_FILTER_EN_CH0 RX_FILTER_THRES_CH0 REF_CNT_RST_CH0 REF_ALWAYS_ON_CH0 IDLE_OUT_LV_CH0 IDLE_OUT_EN_CH0

TX_START_CH0 :
bits : 0 - 0 (1 bit)

RX_EN_CH0 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH0 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH0 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH0 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH0 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH0 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH0 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH0 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH0 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH0 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH0 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH0 :
bits : 19 - 19 (1 bit)


CH1CONF0

RMT_CH1CONF0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CONF0 CH1CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH1 IDLE_THRES_CH1 MEM_SIZE_CH1 CARRIER_EN_CH1 CARRIER_OUT_LV_CH1

DIV_CNT_CH1 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH1 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH1 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH1 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH1 :
bits : 29 - 29 (1 bit)


CH1CONF1

RMT_CH1CONF1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CONF1 CH1CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH1 RX_EN_CH1 MEM_WR_RST_CH1 MEM_RD_RST_CH1 APB_MEM_RST_CH1 MEM_OWNER_CH1 TX_CONTI_MODE_CH1 RX_FILTER_EN_CH1 RX_FILTER_THRES_CH1 REF_CNT_RST_CH1 REF_ALWAYS_ON_CH1 IDLE_OUT_LV_CH1 IDLE_OUT_EN_CH1

TX_START_CH1 :
bits : 0 - 0 (1 bit)

RX_EN_CH1 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH1 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH1 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH1 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH1 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH1 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH1 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH1 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH1 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH1 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH1 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH1 :
bits : 19 - 19 (1 bit)


CH2CONF0

RMT_CH2CONF0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CONF0 CH2CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH2 IDLE_THRES_CH2 MEM_SIZE_CH2 CARRIER_EN_CH2 CARRIER_OUT_LV_CH2

DIV_CNT_CH2 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH2 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH2 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH2 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH2 :
bits : 29 - 29 (1 bit)


CH2CONF1

RMT_CH2CONF1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CONF1 CH2CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH2 RX_EN_CH2 MEM_WR_RST_CH2 MEM_RD_RST_CH2 APB_MEM_RST_CH2 MEM_OWNER_CH2 TX_CONTI_MODE_CH2 RX_FILTER_EN_CH2 RX_FILTER_THRES_CH2 REF_CNT_RST_CH2 REF_ALWAYS_ON_CH2 IDLE_OUT_LV_CH2 IDLE_OUT_EN_CH2

TX_START_CH2 :
bits : 0 - 0 (1 bit)

RX_EN_CH2 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH2 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH2 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH2 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH2 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH2 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH2 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH2 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH2 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH2 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH2 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH2 :
bits : 19 - 19 (1 bit)


CH3CONF0

RMT_CH3CONF0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CONF0 CH3CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH3 IDLE_THRES_CH3 MEM_SIZE_CH3 CARRIER_EN_CH3 CARRIER_OUT_LV_CH3

DIV_CNT_CH3 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH3 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH3 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH3 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH3 :
bits : 29 - 29 (1 bit)


CH3CONF1

RMT_CH3CONF1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CONF1 CH3CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH3 RX_EN_CH3 MEM_WR_RST_CH3 MEM_RD_RST_CH3 APB_MEM_RST_CH3 MEM_OWNER_CH3 TX_CONTI_MODE_CH3 RX_FILTER_EN_CH3 RX_FILTER_THRES_CH3 REF_CNT_RST_CH3 REF_ALWAYS_ON_CH3 IDLE_OUT_LV_CH3 IDLE_OUT_EN_CH3

TX_START_CH3 :
bits : 0 - 0 (1 bit)

RX_EN_CH3 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH3 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH3 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH3 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH3 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH3 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH3 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH3 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH3 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH3 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH3 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH3 :
bits : 19 - 19 (1 bit)


CH4CONF0

RMT_CH4CONF0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CONF0 CH4CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH4 IDLE_THRES_CH4 MEM_SIZE_CH4 CARRIER_EN_CH4 CARRIER_OUT_LV_CH4

DIV_CNT_CH4 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH4 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH4 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH4 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH4 :
bits : 29 - 29 (1 bit)


CH4CONF1

RMT_CH4CONF1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CONF1 CH4CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH4 RX_EN_CH4 MEM_WR_RST_CH4 MEM_RD_RST_CH4 APB_MEM_RST_CH4 MEM_OWNER_CH4 TX_CONTI_MODE_CH4 RX_FILTER_EN_CH4 RX_FILTER_THRES_CH4 REF_CNT_RST_CH4 REF_ALWAYS_ON_CH4 IDLE_OUT_LV_CH4 IDLE_OUT_EN_CH4

TX_START_CH4 :
bits : 0 - 0 (1 bit)

RX_EN_CH4 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH4 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH4 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH4 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH4 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH4 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH4 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH4 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH4 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH4 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH4 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH4 :
bits : 19 - 19 (1 bit)


CH5CONF0

RMT_CH5CONF0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CONF0 CH5CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH5 IDLE_THRES_CH5 MEM_SIZE_CH5 CARRIER_EN_CH5 CARRIER_OUT_LV_CH5

DIV_CNT_CH5 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH5 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH5 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH5 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH5 :
bits : 29 - 29 (1 bit)


CH5CONF1

RMT_CH5CONF1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CONF1 CH5CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH5 RX_EN_CH5 MEM_WR_RST_CH5 MEM_RD_RST_CH5 APB_MEM_RST_CH5 MEM_OWNER_CH5 TX_CONTI_MODE_CH5 RX_FILTER_EN_CH5 RX_FILTER_THRES_CH5 REF_CNT_RST_CH5 REF_ALWAYS_ON_CH5 IDLE_OUT_LV_CH5 IDLE_OUT_EN_CH5

TX_START_CH5 :
bits : 0 - 0 (1 bit)

RX_EN_CH5 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH5 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH5 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH5 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH5 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH5 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH5 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH5 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH5 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH5 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH5 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH5 :
bits : 19 - 19 (1 bit)


CH6CONF0

RMT_CH6CONF0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CONF0 CH6CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH6 IDLE_THRES_CH6 MEM_SIZE_CH6 CARRIER_EN_CH6 CARRIER_OUT_LV_CH6

DIV_CNT_CH6 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH6 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH6 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH6 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH6 :
bits : 29 - 29 (1 bit)


CH6CONF1

RMT_CH6CONF1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CONF1 CH6CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH6 RX_EN_CH6 MEM_WR_RST_CH6 MEM_RD_RST_CH6 APB_MEM_RST_CH6 MEM_OWNER_CH6 TX_CONTI_MODE_CH6 RX_FILTER_EN_CH6 RX_FILTER_THRES_CH6 REF_CNT_RST_CH6 REF_ALWAYS_ON_CH6 IDLE_OUT_LV_CH6 IDLE_OUT_EN_CH6

TX_START_CH6 :
bits : 0 - 0 (1 bit)

RX_EN_CH6 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH6 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH6 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH6 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH6 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH6 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH6 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH6 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH6 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH6 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH6 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH6 :
bits : 19 - 19 (1 bit)


CH7CONF0

RMT_CH7CONF0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CONF0 CH7CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_CNT_CH7 IDLE_THRES_CH7 MEM_SIZE_CH7 CARRIER_EN_CH7 CARRIER_OUT_LV_CH7

DIV_CNT_CH7 :
bits : 0 - 7 (8 bit)

IDLE_THRES_CH7 :
bits : 8 - 23 (16 bit)

MEM_SIZE_CH7 :
bits : 24 - 27 (4 bit)

CARRIER_EN_CH7 :
bits : 28 - 28 (1 bit)

CARRIER_OUT_LV_CH7 :
bits : 29 - 29 (1 bit)


CH7CONF1

RMT_CH7CONF1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CONF1 CH7CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_START_CH7 RX_EN_CH7 MEM_WR_RST_CH7 MEM_RD_RST_CH7 APB_MEM_RST_CH7 MEM_OWNER_CH7 TX_CONTI_MODE_CH7 RX_FILTER_EN_CH7 RX_FILTER_THRES_CH7 REF_CNT_RST_CH7 REF_ALWAYS_ON_CH7 IDLE_OUT_LV_CH7 IDLE_OUT_EN_CH7

TX_START_CH7 :
bits : 0 - 0 (1 bit)

RX_EN_CH7 :
bits : 1 - 1 (1 bit)

MEM_WR_RST_CH7 :
bits : 2 - 2 (1 bit)

MEM_RD_RST_CH7 :
bits : 3 - 3 (1 bit)

APB_MEM_RST_CH7 :
bits : 4 - 4 (1 bit)

MEM_OWNER_CH7 :
bits : 5 - 5 (1 bit)

TX_CONTI_MODE_CH7 :
bits : 6 - 6 (1 bit)

RX_FILTER_EN_CH7 :
bits : 7 - 7 (1 bit)

RX_FILTER_THRES_CH7 :
bits : 8 - 15 (8 bit)

REF_CNT_RST_CH7 :
bits : 16 - 16 (1 bit)

REF_ALWAYS_ON_CH7 :
bits : 17 - 17 (1 bit)

IDLE_OUT_LV_CH7 :
bits : 18 - 18 (1 bit)

IDLE_OUT_EN_CH7 :
bits : 19 - 19 (1 bit)


CH0STATUS

RMT_CH0STATUS
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0STATUS CH0STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH0 MEM_WADDR_EX_CH0 MEM_RADDR_EX_CH0 STATE_CH0 MEM_OWNER_ERR_CH0 MEM_FULL_CH0 MEM_EMPTY_CH0 APB_MEM_WR_ERR_CH0 APB_MEM_RD_ERR_CH0

STATUS_CH0 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH0 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH0 :
bits : 12 - 21 (10 bit)

STATE_CH0 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH0 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH0 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH0 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH0 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH0 :
bits : 31 - 31 (1 bit)


CH1STATUS

RMT_CH1STATUS
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1STATUS CH1STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH1 MEM_WADDR_EX_CH1 MEM_RADDR_EX_CH1 STATE_CH1 MEM_OWNER_ERR_CH1 MEM_FULL_CH1 MEM_EMPTY_CH1 APB_MEM_WR_ERR_CH1 APB_MEM_RD_ERR_CH1

STATUS_CH1 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH1 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH1 :
bits : 12 - 21 (10 bit)

STATE_CH1 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH1 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH1 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH1 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH1 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH1 :
bits : 31 - 31 (1 bit)


CH2STATUS

RMT_CH2STATUS
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2STATUS CH2STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH2 MEM_WADDR_EX_CH2 MEM_RADDR_EX_CH2 STATE_CH2 MEM_OWNER_ERR_CH2 MEM_FULL_CH2 MEM_EMPTY_CH2 APB_MEM_WR_ERR_CH2 APB_MEM_RD_ERR_CH2

STATUS_CH2 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH2 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH2 :
bits : 12 - 21 (10 bit)

STATE_CH2 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH2 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH2 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH2 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH2 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH2 :
bits : 31 - 31 (1 bit)


CH3STATUS

RMT_CH3STATUS
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3STATUS CH3STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH3 MEM_WADDR_EX_CH3 MEM_RADDR_EX_CH3 STATE_CH3 MEM_OWNER_ERR_CH3 MEM_FULL_CH3 MEM_EMPTY_CH3 APB_MEM_WR_ERR_CH3 APB_MEM_RD_ERR_CH3

STATUS_CH3 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH3 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH3 :
bits : 12 - 21 (10 bit)

STATE_CH3 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH3 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH3 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH3 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH3 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH3 :
bits : 31 - 31 (1 bit)


CH4STATUS

RMT_CH4STATUS
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4STATUS CH4STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH4 MEM_WADDR_EX_CH4 MEM_RADDR_EX_CH4 STATE_CH4 MEM_OWNER_ERR_CH4 MEM_FULL_CH4 MEM_EMPTY_CH4 APB_MEM_WR_ERR_CH4 APB_MEM_RD_ERR_CH4

STATUS_CH4 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH4 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH4 :
bits : 12 - 21 (10 bit)

STATE_CH4 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH4 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH4 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH4 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH4 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH4 :
bits : 31 - 31 (1 bit)


CH5STATUS

RMT_CH5STATUS
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5STATUS CH5STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH5 MEM_WADDR_EX_CH5 MEM_RADDR_EX_CH5 STATE_CH5 MEM_OWNER_ERR_CH5 MEM_FULL_CH5 MEM_EMPTY_CH5 APB_MEM_WR_ERR_CH5 APB_MEM_RD_ERR_CH5

STATUS_CH5 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH5 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH5 :
bits : 12 - 21 (10 bit)

STATE_CH5 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH5 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH5 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH5 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH5 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH5 :
bits : 31 - 31 (1 bit)


CH6STATUS

RMT_CH6STATUS
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6STATUS CH6STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH6 MEM_WADDR_EX_CH6 MEM_RADDR_EX_CH6 STATE_CH6 MEM_OWNER_ERR_CH6 MEM_FULL_CH6 MEM_EMPTY_CH6 APB_MEM_WR_ERR_CH6 APB_MEM_RD_ERR_CH6

STATUS_CH6 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH6 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH6 :
bits : 12 - 21 (10 bit)

STATE_CH6 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH6 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH6 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH6 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH6 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH6 :
bits : 31 - 31 (1 bit)


CH7STATUS

RMT_CH7STATUS
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7STATUS CH7STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_CH7 MEM_WADDR_EX_CH7 MEM_RADDR_EX_CH7 STATE_CH7 MEM_OWNER_ERR_CH7 MEM_FULL_CH7 MEM_EMPTY_CH7 APB_MEM_WR_ERR_CH7 APB_MEM_RD_ERR_CH7

STATUS_CH7 :
bits : 0 - 31 (32 bit)

MEM_WADDR_EX_CH7 :
bits : 0 - 9 (10 bit)

MEM_RADDR_EX_CH7 :
bits : 12 - 21 (10 bit)

STATE_CH7 :
bits : 24 - 26 (3 bit)

MEM_OWNER_ERR_CH7 :
bits : 27 - 27 (1 bit)

MEM_FULL_CH7 :
bits : 28 - 28 (1 bit)

MEM_EMPTY_CH7 :
bits : 29 - 29 (1 bit)

APB_MEM_WR_ERR_CH7 :
bits : 30 - 30 (1 bit)

APB_MEM_RD_ERR_CH7 :
bits : 31 - 31 (1 bit)


CH0ADDR

RMT_CH0ADDR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0ADDR CH0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH0

APB_MEM_ADDR_CH0 :
bits : 0 - 31 (32 bit)


CH1ADDR

RMT_CH1ADDR
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1ADDR CH1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH1

APB_MEM_ADDR_CH1 :
bits : 0 - 31 (32 bit)


CH2ADDR

RMT_CH2ADDR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2ADDR CH2ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH2

APB_MEM_ADDR_CH2 :
bits : 0 - 31 (32 bit)


CH3ADDR

RMT_CH3ADDR
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3ADDR CH3ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH3

APB_MEM_ADDR_CH3 :
bits : 0 - 31 (32 bit)


CH4ADDR

RMT_CH4ADDR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4ADDR CH4ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH4

APB_MEM_ADDR_CH4 :
bits : 0 - 31 (32 bit)


CH5ADDR

RMT_CH5ADDR
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5ADDR CH5ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH5

APB_MEM_ADDR_CH5 :
bits : 0 - 31 (32 bit)


CH6ADDR

RMT_CH6ADDR
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6ADDR CH6ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH6

APB_MEM_ADDR_CH6 :
bits : 0 - 31 (32 bit)


CH7ADDR

RMT_CH7ADDR
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7ADDR CH7ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_MEM_ADDR_CH7

APB_MEM_ADDR_CH7 :
bits : 0 - 31 (32 bit)


INT_RAW

RMT_INT_RAW
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_TX_END_INT_RAW CH0_RX_END_INT_RAW CH0_ERR_INT_RAW CH1_TX_END_INT_RAW CH1_RX_END_INT_RAW CH1_ERR_INT_RAW CH2_TX_END_INT_RAW CH2_RX_END_INT_RAW CH2_ERR_INT_RAW CH3_TX_END_INT_RAW CH3_RX_END_INT_RAW CH3_ERR_INT_RAW CH4_TX_END_INT_RAW CH4_RX_END_INT_RAW CH4_ERR_INT_RAW CH5_TX_END_INT_RAW CH5_RX_END_INT_RAW CH5_ERR_INT_RAW CH6_TX_END_INT_RAW CH6_RX_END_INT_RAW CH6_ERR_INT_RAW CH7_TX_END_INT_RAW CH7_RX_END_INT_RAW CH7_ERR_INT_RAW CH0_TX_THR_EVENT_INT_RAW CH1_TX_THR_EVENT_INT_RAW CH2_TX_THR_EVENT_INT_RAW CH3_TX_THR_EVENT_INT_RAW CH4_TX_THR_EVENT_INT_RAW CH5_TX_THR_EVENT_INT_RAW CH6_TX_THR_EVENT_INT_RAW CH7_TX_THR_EVENT_INT_RAW

CH0_TX_END_INT_RAW :
bits : 0 - 0 (1 bit)

CH0_RX_END_INT_RAW :
bits : 1 - 1 (1 bit)

CH0_ERR_INT_RAW :
bits : 2 - 2 (1 bit)

CH1_TX_END_INT_RAW :
bits : 3 - 3 (1 bit)

CH1_RX_END_INT_RAW :
bits : 4 - 4 (1 bit)

CH1_ERR_INT_RAW :
bits : 5 - 5 (1 bit)

CH2_TX_END_INT_RAW :
bits : 6 - 6 (1 bit)

CH2_RX_END_INT_RAW :
bits : 7 - 7 (1 bit)

CH2_ERR_INT_RAW :
bits : 8 - 8 (1 bit)

CH3_TX_END_INT_RAW :
bits : 9 - 9 (1 bit)

CH3_RX_END_INT_RAW :
bits : 10 - 10 (1 bit)

CH3_ERR_INT_RAW :
bits : 11 - 11 (1 bit)

CH4_TX_END_INT_RAW :
bits : 12 - 12 (1 bit)

CH4_RX_END_INT_RAW :
bits : 13 - 13 (1 bit)

CH4_ERR_INT_RAW :
bits : 14 - 14 (1 bit)

CH5_TX_END_INT_RAW :
bits : 15 - 15 (1 bit)

CH5_RX_END_INT_RAW :
bits : 16 - 16 (1 bit)

CH5_ERR_INT_RAW :
bits : 17 - 17 (1 bit)

CH6_TX_END_INT_RAW :
bits : 18 - 18 (1 bit)

CH6_RX_END_INT_RAW :
bits : 19 - 19 (1 bit)

CH6_ERR_INT_RAW :
bits : 20 - 20 (1 bit)

CH7_TX_END_INT_RAW :
bits : 21 - 21 (1 bit)

CH7_RX_END_INT_RAW :
bits : 22 - 22 (1 bit)

CH7_ERR_INT_RAW :
bits : 23 - 23 (1 bit)

CH0_TX_THR_EVENT_INT_RAW :
bits : 24 - 24 (1 bit)

CH1_TX_THR_EVENT_INT_RAW :
bits : 25 - 25 (1 bit)

CH2_TX_THR_EVENT_INT_RAW :
bits : 26 - 26 (1 bit)

CH3_TX_THR_EVENT_INT_RAW :
bits : 27 - 27 (1 bit)

CH4_TX_THR_EVENT_INT_RAW :
bits : 28 - 28 (1 bit)

CH5_TX_THR_EVENT_INT_RAW :
bits : 29 - 29 (1 bit)

CH6_TX_THR_EVENT_INT_RAW :
bits : 30 - 30 (1 bit)

CH7_TX_THR_EVENT_INT_RAW :
bits : 31 - 31 (1 bit)


INT_ST

RMT_INT_ST
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ST INT_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_TX_END_INT_ST CH0_RX_END_INT_ST CH0_ERR_INT_ST CH1_TX_END_INT_ST CH1_RX_END_INT_ST CH1_ERR_INT_ST CH2_TX_END_INT_ST CH2_RX_END_INT_ST CH2_ERR_INT_ST CH3_TX_END_INT_ST CH3_RX_END_INT_ST CH3_ERR_INT_ST CH4_TX_END_INT_ST CH4_RX_END_INT_ST CH4_ERR_INT_ST CH5_TX_END_INT_ST CH5_RX_END_INT_ST CH5_ERR_INT_ST CH6_TX_END_INT_ST CH6_RX_END_INT_ST CH6_ERR_INT_ST CH7_TX_END_INT_ST CH7_RX_END_INT_ST CH7_ERR_INT_ST CH0_TX_THR_EVENT_INT_ST CH1_TX_THR_EVENT_INT_ST CH2_TX_THR_EVENT_INT_ST CH3_TX_THR_EVENT_INT_ST CH4_TX_THR_EVENT_INT_ST CH5_TX_THR_EVENT_INT_ST CH6_TX_THR_EVENT_INT_ST CH7_TX_THR_EVENT_INT_ST

CH0_TX_END_INT_ST :
bits : 0 - 0 (1 bit)

CH0_RX_END_INT_ST :
bits : 1 - 1 (1 bit)

CH0_ERR_INT_ST :
bits : 2 - 2 (1 bit)

CH1_TX_END_INT_ST :
bits : 3 - 3 (1 bit)

CH1_RX_END_INT_ST :
bits : 4 - 4 (1 bit)

CH1_ERR_INT_ST :
bits : 5 - 5 (1 bit)

CH2_TX_END_INT_ST :
bits : 6 - 6 (1 bit)

CH2_RX_END_INT_ST :
bits : 7 - 7 (1 bit)

CH2_ERR_INT_ST :
bits : 8 - 8 (1 bit)

CH3_TX_END_INT_ST :
bits : 9 - 9 (1 bit)

CH3_RX_END_INT_ST :
bits : 10 - 10 (1 bit)

CH3_ERR_INT_ST :
bits : 11 - 11 (1 bit)

CH4_TX_END_INT_ST :
bits : 12 - 12 (1 bit)

CH4_RX_END_INT_ST :
bits : 13 - 13 (1 bit)

CH4_ERR_INT_ST :
bits : 14 - 14 (1 bit)

CH5_TX_END_INT_ST :
bits : 15 - 15 (1 bit)

CH5_RX_END_INT_ST :
bits : 16 - 16 (1 bit)

CH5_ERR_INT_ST :
bits : 17 - 17 (1 bit)

CH6_TX_END_INT_ST :
bits : 18 - 18 (1 bit)

CH6_RX_END_INT_ST :
bits : 19 - 19 (1 bit)

CH6_ERR_INT_ST :
bits : 20 - 20 (1 bit)

CH7_TX_END_INT_ST :
bits : 21 - 21 (1 bit)

CH7_RX_END_INT_ST :
bits : 22 - 22 (1 bit)

CH7_ERR_INT_ST :
bits : 23 - 23 (1 bit)

CH0_TX_THR_EVENT_INT_ST :
bits : 24 - 24 (1 bit)

CH1_TX_THR_EVENT_INT_ST :
bits : 25 - 25 (1 bit)

CH2_TX_THR_EVENT_INT_ST :
bits : 26 - 26 (1 bit)

CH3_TX_THR_EVENT_INT_ST :
bits : 27 - 27 (1 bit)

CH4_TX_THR_EVENT_INT_ST :
bits : 28 - 28 (1 bit)

CH5_TX_THR_EVENT_INT_ST :
bits : 29 - 29 (1 bit)

CH6_TX_THR_EVENT_INT_ST :
bits : 30 - 30 (1 bit)

CH7_TX_THR_EVENT_INT_ST :
bits : 31 - 31 (1 bit)


INT_ENA

RMT_INT_ENA
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_TX_END_INT_ENA CH0_RX_END_INT_ENA CH0_ERR_INT_ENA CH1_TX_END_INT_ENA CH1_RX_END_INT_ENA CH1_ERR_INT_ENA CH2_TX_END_INT_ENA CH2_RX_END_INT_ENA CH2_ERR_INT_ENA CH3_TX_END_INT_ENA CH3_RX_END_INT_ENA CH3_ERR_INT_ENA CH4_TX_END_INT_ENA CH4_RX_END_INT_ENA CH4_ERR_INT_ENA CH5_TX_END_INT_ENA CH5_RX_END_INT_ENA CH5_ERR_INT_ENA CH6_TX_END_INT_ENA CH6_RX_END_INT_ENA CH6_ERR_INT_ENA CH7_TX_END_INT_ENA CH7_RX_END_INT_ENA CH7_ERR_INT_ENA CH0_TX_THR_EVENT_INT_ENA CH1_TX_THR_EVENT_INT_ENA CH2_TX_THR_EVENT_INT_ENA CH3_TX_THR_EVENT_INT_ENA CH4_TX_THR_EVENT_INT_ENA CH5_TX_THR_EVENT_INT_ENA CH6_TX_THR_EVENT_INT_ENA CH7_TX_THR_EVENT_INT_ENA

CH0_TX_END_INT_ENA :
bits : 0 - 0 (1 bit)

CH0_RX_END_INT_ENA :
bits : 1 - 1 (1 bit)

CH0_ERR_INT_ENA :
bits : 2 - 2 (1 bit)

CH1_TX_END_INT_ENA :
bits : 3 - 3 (1 bit)

CH1_RX_END_INT_ENA :
bits : 4 - 4 (1 bit)

CH1_ERR_INT_ENA :
bits : 5 - 5 (1 bit)

CH2_TX_END_INT_ENA :
bits : 6 - 6 (1 bit)

CH2_RX_END_INT_ENA :
bits : 7 - 7 (1 bit)

CH2_ERR_INT_ENA :
bits : 8 - 8 (1 bit)

CH3_TX_END_INT_ENA :
bits : 9 - 9 (1 bit)

CH3_RX_END_INT_ENA :
bits : 10 - 10 (1 bit)

CH3_ERR_INT_ENA :
bits : 11 - 11 (1 bit)

CH4_TX_END_INT_ENA :
bits : 12 - 12 (1 bit)

CH4_RX_END_INT_ENA :
bits : 13 - 13 (1 bit)

CH4_ERR_INT_ENA :
bits : 14 - 14 (1 bit)

CH5_TX_END_INT_ENA :
bits : 15 - 15 (1 bit)

CH5_RX_END_INT_ENA :
bits : 16 - 16 (1 bit)

CH5_ERR_INT_ENA :
bits : 17 - 17 (1 bit)

CH6_TX_END_INT_ENA :
bits : 18 - 18 (1 bit)

CH6_RX_END_INT_ENA :
bits : 19 - 19 (1 bit)

CH6_ERR_INT_ENA :
bits : 20 - 20 (1 bit)

CH7_TX_END_INT_ENA :
bits : 21 - 21 (1 bit)

CH7_RX_END_INT_ENA :
bits : 22 - 22 (1 bit)

CH7_ERR_INT_ENA :
bits : 23 - 23 (1 bit)

CH0_TX_THR_EVENT_INT_ENA :
bits : 24 - 24 (1 bit)

CH1_TX_THR_EVENT_INT_ENA :
bits : 25 - 25 (1 bit)

CH2_TX_THR_EVENT_INT_ENA :
bits : 26 - 26 (1 bit)

CH3_TX_THR_EVENT_INT_ENA :
bits : 27 - 27 (1 bit)

CH4_TX_THR_EVENT_INT_ENA :
bits : 28 - 28 (1 bit)

CH5_TX_THR_EVENT_INT_ENA :
bits : 29 - 29 (1 bit)

CH6_TX_THR_EVENT_INT_ENA :
bits : 30 - 30 (1 bit)

CH7_TX_THR_EVENT_INT_ENA :
bits : 31 - 31 (1 bit)


INT_CLR

RMT_INT_CLR
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_TX_END_INT_CLR CH0_RX_END_INT_CLR CH0_ERR_INT_CLR CH1_TX_END_INT_CLR CH1_RX_END_INT_CLR CH1_ERR_INT_CLR CH2_TX_END_INT_CLR CH2_RX_END_INT_CLR CH2_ERR_INT_CLR CH3_TX_END_INT_CLR CH3_RX_END_INT_CLR CH3_ERR_INT_CLR CH4_TX_END_INT_CLR CH4_RX_END_INT_CLR CH4_ERR_INT_CLR CH5_TX_END_INT_CLR CH5_RX_END_INT_CLR CH5_ERR_INT_CLR CH6_TX_END_INT_CLR CH6_RX_END_INT_CLR CH6_ERR_INT_CLR CH7_TX_END_INT_CLR CH7_RX_END_INT_CLR CH7_ERR_INT_CLR CH0_TX_THR_EVENT_INT_CLR CH1_TX_THR_EVENT_INT_CLR CH2_TX_THR_EVENT_INT_CLR CH3_TX_THR_EVENT_INT_CLR CH4_TX_THR_EVENT_INT_CLR CH5_TX_THR_EVENT_INT_CLR CH6_TX_THR_EVENT_INT_CLR CH7_TX_THR_EVENT_INT_CLR

CH0_TX_END_INT_CLR :
bits : 0 - 0 (1 bit)

CH0_RX_END_INT_CLR :
bits : 1 - 1 (1 bit)

CH0_ERR_INT_CLR :
bits : 2 - 2 (1 bit)

CH1_TX_END_INT_CLR :
bits : 3 - 3 (1 bit)

CH1_RX_END_INT_CLR :
bits : 4 - 4 (1 bit)

CH1_ERR_INT_CLR :
bits : 5 - 5 (1 bit)

CH2_TX_END_INT_CLR :
bits : 6 - 6 (1 bit)

CH2_RX_END_INT_CLR :
bits : 7 - 7 (1 bit)

CH2_ERR_INT_CLR :
bits : 8 - 8 (1 bit)

CH3_TX_END_INT_CLR :
bits : 9 - 9 (1 bit)

CH3_RX_END_INT_CLR :
bits : 10 - 10 (1 bit)

CH3_ERR_INT_CLR :
bits : 11 - 11 (1 bit)

CH4_TX_END_INT_CLR :
bits : 12 - 12 (1 bit)

CH4_RX_END_INT_CLR :
bits : 13 - 13 (1 bit)

CH4_ERR_INT_CLR :
bits : 14 - 14 (1 bit)

CH5_TX_END_INT_CLR :
bits : 15 - 15 (1 bit)

CH5_RX_END_INT_CLR :
bits : 16 - 16 (1 bit)

CH5_ERR_INT_CLR :
bits : 17 - 17 (1 bit)

CH6_TX_END_INT_CLR :
bits : 18 - 18 (1 bit)

CH6_RX_END_INT_CLR :
bits : 19 - 19 (1 bit)

CH6_ERR_INT_CLR :
bits : 20 - 20 (1 bit)

CH7_TX_END_INT_CLR :
bits : 21 - 21 (1 bit)

CH7_RX_END_INT_CLR :
bits : 22 - 22 (1 bit)

CH7_ERR_INT_CLR :
bits : 23 - 23 (1 bit)

CH0_TX_THR_EVENT_INT_CLR :
bits : 24 - 24 (1 bit)

CH1_TX_THR_EVENT_INT_CLR :
bits : 25 - 25 (1 bit)

CH2_TX_THR_EVENT_INT_CLR :
bits : 26 - 26 (1 bit)

CH3_TX_THR_EVENT_INT_CLR :
bits : 27 - 27 (1 bit)

CH4_TX_THR_EVENT_INT_CLR :
bits : 28 - 28 (1 bit)

CH5_TX_THR_EVENT_INT_CLR :
bits : 29 - 29 (1 bit)

CH6_TX_THR_EVENT_INT_CLR :
bits : 30 - 30 (1 bit)

CH7_TX_THR_EVENT_INT_CLR :
bits : 31 - 31 (1 bit)


CH0CARRIER_DUTY

RMT_CH0CARRIER_DUTY
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CARRIER_DUTY CH0CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH0 CARRIER_HIGH_CH0

CARRIER_LOW_CH0 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH0 :
bits : 16 - 31 (16 bit)


CH1CARRIER_DUTY

RMT_CH1CARRIER_DUTY
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CARRIER_DUTY CH1CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH1 CARRIER_HIGH_CH1

CARRIER_LOW_CH1 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH1 :
bits : 16 - 31 (16 bit)


CH2CARRIER_DUTY

RMT_CH2CARRIER_DUTY
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CARRIER_DUTY CH2CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH2 CARRIER_HIGH_CH2

CARRIER_LOW_CH2 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH2 :
bits : 16 - 31 (16 bit)


CH3CARRIER_DUTY

RMT_CH3CARRIER_DUTY
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CARRIER_DUTY CH3CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH3 CARRIER_HIGH_CH3

CARRIER_LOW_CH3 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH3 :
bits : 16 - 31 (16 bit)


CH4CARRIER_DUTY

RMT_CH4CARRIER_DUTY
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CARRIER_DUTY CH4CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH4 CARRIER_HIGH_CH4

CARRIER_LOW_CH4 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH4 :
bits : 16 - 31 (16 bit)


CH5CARRIER_DUTY

RMT_CH5CARRIER_DUTY
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CARRIER_DUTY CH5CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH5 CARRIER_HIGH_CH5

CARRIER_LOW_CH5 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH5 :
bits : 16 - 31 (16 bit)


CH6CARRIER_DUTY

RMT_CH6CARRIER_DUTY
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CARRIER_DUTY CH6CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH6 CARRIER_HIGH_CH6

CARRIER_LOW_CH6 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH6 :
bits : 16 - 31 (16 bit)


CH7CARRIER_DUTY

RMT_CH7CARRIER_DUTY
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CARRIER_DUTY CH7CARRIER_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER_LOW_CH7 CARRIER_HIGH_CH7

CARRIER_LOW_CH7 :
bits : 0 - 15 (16 bit)

CARRIER_HIGH_CH7 :
bits : 16 - 31 (16 bit)


CH0_TX_LIM

RMT_CH0_TX_LIM
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_TX_LIM CH0_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH0

TX_LIM_CH0 :
bits : 0 - 8 (9 bit)


CH1_TX_LIM

RMT_CH1_TX_LIM
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_TX_LIM CH1_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH1

TX_LIM_CH1 :
bits : 0 - 8 (9 bit)


CH2_TX_LIM

RMT_CH2_TX_LIM
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_TX_LIM CH2_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH2

TX_LIM_CH2 :
bits : 0 - 8 (9 bit)


CH3_TX_LIM

RMT_CH3_TX_LIM
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_TX_LIM CH3_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH3

TX_LIM_CH3 :
bits : 0 - 8 (9 bit)


CH4_TX_LIM

RMT_CH4_TX_LIM
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_TX_LIM CH4_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH4

TX_LIM_CH4 :
bits : 0 - 8 (9 bit)


CH5_TX_LIM

RMT_CH5_TX_LIM
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_TX_LIM CH5_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH5

TX_LIM_CH5 :
bits : 0 - 8 (9 bit)


CH6_TX_LIM

RMT_CH6_TX_LIM
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_TX_LIM CH6_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH6

TX_LIM_CH6 :
bits : 0 - 8 (9 bit)


CH7_TX_LIM

RMT_CH7_TX_LIM
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_TX_LIM CH7_TX_LIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_LIM_CH7

TX_LIM_CH7 :
bits : 0 - 8 (9 bit)


APB_CONF

RMT_APB_CONF
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB_CONF APB_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_FIFO_MASK MEM_TX_WRAP_EN

APB_FIFO_MASK :
bits : 0 - 0 (1 bit)

MEM_TX_WRAP_EN :
bits : 1 - 1 (1 bit)


DATE

RMT_DATE
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 31 (32 bit)



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