\n
address_offset : 0x0 Bytes (0x0)
size : 0x620 byte (0x0)
mem_usage : registers
protection : not protected
UHCI_CONF0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_RST :
bits : 0 - 0 (1 bit)
OUT_RST :
bits : 1 - 1 (1 bit)
AHBM_FIFO_RST :
bits : 2 - 2 (1 bit)
AHBM_RST :
bits : 3 - 3 (1 bit)
IN_LOOP_TEST :
bits : 4 - 4 (1 bit)
OUT_LOOP_TEST :
bits : 5 - 5 (1 bit)
OUT_AUTO_WRBACK :
bits : 6 - 6 (1 bit)
OUT_NO_RESTART_CLR :
bits : 7 - 7 (1 bit)
OUT_EOF_MODE :
bits : 8 - 8 (1 bit)
UART0_CE :
bits : 9 - 9 (1 bit)
UART1_CE :
bits : 10 - 10 (1 bit)
UART2_CE :
bits : 11 - 11 (1 bit)
OUTDSCR_BURST_EN :
bits : 12 - 12 (1 bit)
INDSCR_BURST_EN :
bits : 13 - 13 (1 bit)
OUT_DATA_BURST_EN :
bits : 14 - 14 (1 bit)
MEM_TRANS_EN :
bits : 15 - 15 (1 bit)
SEPER_EN :
bits : 16 - 16 (1 bit)
HEAD_EN :
bits : 17 - 17 (1 bit)
CRC_REC_EN :
bits : 18 - 18 (1 bit)
UART_IDLE_EOF_EN :
bits : 19 - 19 (1 bit)
LEN_EOF_EN :
bits : 20 - 20 (1 bit)
ENCODE_CRC_EN :
bits : 21 - 21 (1 bit)
CLK_EN :
bits : 22 - 22 (1 bit)
UART_RX_BRK_EOF_EN :
bits : 23 - 23 (1 bit)
UHCI_INT_CLR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_START_INT_CLR :
bits : 0 - 0 (1 bit)
TX_START_INT_CLR :
bits : 1 - 1 (1 bit)
RX_HUNG_INT_CLR :
bits : 2 - 2 (1 bit)
TX_HUNG_INT_CLR :
bits : 3 - 3 (1 bit)
IN_DONE_INT_CLR :
bits : 4 - 4 (1 bit)
IN_SUC_EOF_INT_CLR :
bits : 5 - 5 (1 bit)
IN_ERR_EOF_INT_CLR :
bits : 6 - 6 (1 bit)
OUT_DONE_INT_CLR :
bits : 7 - 7 (1 bit)
OUT_EOF_INT_CLR :
bits : 8 - 8 (1 bit)
IN_DSCR_ERR_INT_CLR :
bits : 9 - 9 (1 bit)
OUT_DSCR_ERR_INT_CLR :
bits : 10 - 10 (1 bit)
IN_DSCR_EMPTY_INT_CLR :
bits : 11 - 11 (1 bit)
OUTLINK_EOF_ERR_INT_CLR :
bits : 12 - 12 (1 bit)
OUT_TOTAL_EOF_INT_CLR :
bits : 13 - 13 (1 bit)
SEND_S_Q_INT_CLR :
bits : 14 - 14 (1 bit)
SEND_A_Q_INT_CLR :
bits : 15 - 15 (1 bit)
DMA_INFIFO_FULL_WM_INT_CLR :
bits : 16 - 16 (1 bit)
UHCI_DMA_OUT_STATUS
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_FULL :
bits : 0 - 0 (1 bit)
OUT_EMPTY :
bits : 1 - 1 (1 bit)
UHCI_DMA_OUT_PUSH
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTFIFO_WDATA :
bits : 0 - 8 (9 bit)
OUTFIFO_PUSH :
bits : 16 - 16 (1 bit)
UHCI_DMA_IN_STATUS
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_FULL :
bits : 0 - 0 (1 bit)
IN_EMPTY :
bits : 1 - 1 (1 bit)
RX_ERR_CAUSE :
bits : 4 - 6 (3 bit)
UHCI_DMA_IN_POP
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFIFO_RDATA :
bits : 0 - 11 (12 bit)
INFIFO_POP :
bits : 16 - 16 (1 bit)
UHCI_DMA_OUT_LINK
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTLINK_ADDR :
bits : 0 - 19 (20 bit)
OUTLINK_STOP :
bits : 28 - 28 (1 bit)
OUTLINK_START :
bits : 29 - 29 (1 bit)
OUTLINK_RESTART :
bits : 30 - 30 (1 bit)
OUTLINK_PARK :
bits : 31 - 31 (1 bit)
UHCI_DMA_IN_LINK
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INLINK_ADDR :
bits : 0 - 19 (20 bit)
INLINK_AUTO_RET :
bits : 20 - 20 (1 bit)
INLINK_STOP :
bits : 28 - 28 (1 bit)
INLINK_START :
bits : 29 - 29 (1 bit)
INLINK_RESTART :
bits : 30 - 30 (1 bit)
INLINK_PARK :
bits : 31 - 31 (1 bit)
UHCI_CONF1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHECK_SUM_EN :
bits : 0 - 0 (1 bit)
CHECK_SEQ_EN :
bits : 1 - 1 (1 bit)
CRC_DISABLE :
bits : 2 - 2 (1 bit)
SAVE_HEAD :
bits : 3 - 3 (1 bit)
TX_CHECK_SUM_RE :
bits : 4 - 4 (1 bit)
TX_ACK_NUM_RE :
bits : 5 - 5 (1 bit)
CHECK_OWNER :
bits : 6 - 6 (1 bit)
WAIT_SW_START :
bits : 7 - 7 (1 bit)
SW_START :
bits : 8 - 8 (1 bit)
DMA_INFIFO_FULL_THRS :
bits : 9 - 20 (12 bit)
UHCI_STATE0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE0 :
bits : 0 - 31 (32 bit)
UHCI_STATE1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE1 :
bits : 0 - 31 (32 bit)
UHCI_DMA_OUT_EOF_DES_ADDR
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_EOF_DES_ADDR :
bits : 0 - 31 (32 bit)
UHCI_DMA_IN_SUC_EOF_DES_ADDR
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_SUC_EOF_DES_ADDR :
bits : 0 - 31 (32 bit)
UHCI_INT_RAW
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_START_INT_RAW :
bits : 0 - 0 (1 bit)
TX_START_INT_RAW :
bits : 1 - 1 (1 bit)
RX_HUNG_INT_RAW :
bits : 2 - 2 (1 bit)
TX_HUNG_INT_RAW :
bits : 3 - 3 (1 bit)
IN_DONE_INT_RAW :
bits : 4 - 4 (1 bit)
IN_SUC_EOF_INT_RAW :
bits : 5 - 5 (1 bit)
IN_ERR_EOF_INT_RAW :
bits : 6 - 6 (1 bit)
OUT_DONE_INT_RAW :
bits : 7 - 7 (1 bit)
OUT_EOF_INT_RAW :
bits : 8 - 8 (1 bit)
IN_DSCR_ERR_INT_RAW :
bits : 9 - 9 (1 bit)
OUT_DSCR_ERR_INT_RAW :
bits : 10 - 10 (1 bit)
IN_DSCR_EMPTY_INT_RAW :
bits : 11 - 11 (1 bit)
OUTLINK_EOF_ERR_INT_RAW :
bits : 12 - 12 (1 bit)
OUT_TOTAL_EOF_INT_RAW :
bits : 13 - 13 (1 bit)
SEND_S_Q_INT_RAW :
bits : 14 - 14 (1 bit)
SEND_A_Q_INT_RAW :
bits : 15 - 15 (1 bit)
DMA_INFIFO_FULL_WM_INT_RAW :
bits : 16 - 16 (1 bit)
UHCI_DMA_IN_ERR_EOF_DES_ADDR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_ERR_EOF_DES_ADDR :
bits : 0 - 31 (32 bit)
UHCI_DMA_OUT_EOF_BFR_DES_ADDR
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_EOF_BFR_DES_ADDR :
bits : 0 - 31 (32 bit)
UHCI_AHB_TEST
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHB_TESTMODE :
bits : 0 - 2 (3 bit)
AHB_TESTADDR :
bits : 4 - 5 (2 bit)
UHCI_DMA_IN_DSCR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INLINK_DSCR :
bits : 0 - 31 (32 bit)
UHCI_DMA_IN_DSCR_BF0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INLINK_DSCR_BF0 :
bits : 0 - 31 (32 bit)
UHCI_DMA_IN_DSCR_BF1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INLINK_DSCR_BF1 :
bits : 0 - 31 (32 bit)
UHCI_DMA_OUT_DSCR
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTLINK_DSCR :
bits : 0 - 31 (32 bit)
UHCI_DMA_OUT_DSCR_BF0
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTLINK_DSCR_BF0 :
bits : 0 - 31 (32 bit)
UHCI_DMA_OUT_DSCR_BF1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTLINK_DSCR_BF1 :
bits : 0 - 31 (32 bit)
UHCI_ESCAPE_CONF
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_C0_ESC_EN :
bits : 0 - 0 (1 bit)
TX_DB_ESC_EN :
bits : 1 - 1 (1 bit)
TX_11_ESC_EN :
bits : 2 - 2 (1 bit)
TX_13_ESC_EN :
bits : 3 - 3 (1 bit)
RX_C0_ESC_EN :
bits : 4 - 4 (1 bit)
RX_DB_ESC_EN :
bits : 5 - 5 (1 bit)
RX_11_ESC_EN :
bits : 6 - 6 (1 bit)
RX_13_ESC_EN :
bits : 7 - 7 (1 bit)
UHCI_HUNG_CONF
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFIFO_TIMEOUT :
bits : 0 - 7 (8 bit)
TXFIFO_TIMEOUT_SHIFT :
bits : 8 - 10 (3 bit)
TXFIFO_TIMEOUT_ENA :
bits : 11 - 11 (1 bit)
RXFIFO_TIMEOUT :
bits : 12 - 19 (8 bit)
RXFIFO_TIMEOUT_SHIFT :
bits : 20 - 22 (3 bit)
RXFIFO_TIMEOUT_ENA :
bits : 23 - 23 (1 bit)
UHCI_RX_HEAD
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_HEAD :
bits : 0 - 31 (32 bit)
UHCI_QUICK_SENT
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINGLE_SEND_NUM :
bits : 0 - 2 (3 bit)
SINGLE_SEND_EN :
bits : 3 - 3 (1 bit)
ALWAYS_SEND_NUM :
bits : 4 - 6 (3 bit)
ALWAYS_SEND_EN :
bits : 7 - 7 (1 bit)
UHCI_Q0_WORD0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q0_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q0_WORD1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q0_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_INT_ST
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_START_INT_ST :
bits : 0 - 0 (1 bit)
TX_START_INT_ST :
bits : 1 - 1 (1 bit)
RX_HUNG_INT_ST :
bits : 2 - 2 (1 bit)
TX_HUNG_INT_ST :
bits : 3 - 3 (1 bit)
IN_DONE_INT_ST :
bits : 4 - 4 (1 bit)
IN_SUC_EOF_INT_ST :
bits : 5 - 5 (1 bit)
IN_ERR_EOF_INT_ST :
bits : 6 - 6 (1 bit)
OUT_DONE_INT_ST :
bits : 7 - 7 (1 bit)
OUT_EOF_INT_ST :
bits : 8 - 8 (1 bit)
IN_DSCR_ERR_INT_ST :
bits : 9 - 9 (1 bit)
OUT_DSCR_ERR_INT_ST :
bits : 10 - 10 (1 bit)
IN_DSCR_EMPTY_INT_ST :
bits : 11 - 11 (1 bit)
OUTLINK_EOF_ERR_INT_ST :
bits : 12 - 12 (1 bit)
OUT_TOTAL_EOF_INT_ST :
bits : 13 - 13 (1 bit)
SEND_S_Q_INT_ST :
bits : 14 - 14 (1 bit)
SEND_A_Q_INT_ST :
bits : 15 - 15 (1 bit)
DMA_INFIFO_FULL_WM_INT_ST :
bits : 16 - 16 (1 bit)
UHCI_Q1_WORD0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q1_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q1_WORD1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q1_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_Q2_WORD0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q2_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q2_WORD1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q2_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_Q3_WORD0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q3_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q3_WORD1
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q3_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_Q4_WORD0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q4_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q4_WORD1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q4_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_Q5_WORD0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q5_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q5_WORD1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q5_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_Q6_WORD0
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q6_WORD0 :
bits : 0 - 31 (32 bit)
UHCI_Q6_WORD1
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEND_Q6_WORD1 :
bits : 0 - 31 (32 bit)
UHCI_ESC_CONF0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEPER_CHAR :
bits : 0 - 7 (8 bit)
SEPER_ESC_CHAR0 :
bits : 8 - 15 (8 bit)
SEPER_ESC_CHAR1 :
bits : 16 - 23 (8 bit)
UHCI_ESC_CONF1
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESC_SEQ0 :
bits : 0 - 7 (8 bit)
ESC_SEQ0_CHAR0 :
bits : 8 - 15 (8 bit)
ESC_SEQ0_CHAR1 :
bits : 16 - 23 (8 bit)
UHCI_ESC_CONF2
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESC_SEQ1 :
bits : 0 - 7 (8 bit)
ESC_SEQ1_CHAR0 :
bits : 8 - 15 (8 bit)
ESC_SEQ1_CHAR1 :
bits : 16 - 23 (8 bit)
UHCI_ESC_CONF3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESC_SEQ2 :
bits : 0 - 7 (8 bit)
ESC_SEQ2_CHAR0 :
bits : 8 - 15 (8 bit)
ESC_SEQ2_CHAR1 :
bits : 16 - 23 (8 bit)
UHCI_INT_ENA
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_START_INT_ENA :
bits : 0 - 0 (1 bit)
TX_START_INT_ENA :
bits : 1 - 1 (1 bit)
RX_HUNG_INT_ENA :
bits : 2 - 2 (1 bit)
TX_HUNG_INT_ENA :
bits : 3 - 3 (1 bit)
IN_DONE_INT_ENA :
bits : 4 - 4 (1 bit)
IN_SUC_EOF_INT_ENA :
bits : 5 - 5 (1 bit)
IN_ERR_EOF_INT_ENA :
bits : 6 - 6 (1 bit)
OUT_DONE_INT_ENA :
bits : 7 - 7 (1 bit)
OUT_EOF_INT_ENA :
bits : 8 - 8 (1 bit)
IN_DSCR_ERR_INT_ENA :
bits : 9 - 9 (1 bit)
OUT_DSCR_ERR_INT_ENA :
bits : 10 - 10 (1 bit)
IN_DSCR_EMPTY_INT_ENA :
bits : 11 - 11 (1 bit)
OUTLINK_EOF_ERR_INT_ENA :
bits : 12 - 12 (1 bit)
OUT_TOTAL_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
SEND_S_Q_INT_ENA :
bits : 14 - 14 (1 bit)
SEND_A_Q_INT_ENA :
bits : 15 - 15 (1 bit)
DMA_INFIFO_FULL_WM_INT_ENA :
bits : 16 - 16 (1 bit)
UHCI_PKT_THRES
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_THRS :
bits : 0 - 12 (13 bit)
UHCI_DATE
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATE :
bits : 0 - 31 (32 bit)
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