\n
address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected
HOST_SLCHOST_FUNC2_0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC_FUNC2_INT :
bits : 24 - 24 (1 bit)
HOST_SLC_APBWIN_WDATA
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC_APBWIN_WDATA :
bits : 0 - 31 (32 bit)
HOST_SLC_APBWIN_CONF
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC_APBWIN_ADDR :
bits : 0 - 27 (28 bit)
HOST_SLC_APBWIN_WR :
bits : 28 - 28 (1 bit)
HOST_SLC_APBWIN_START :
bits : 29 - 29 (1 bit)
HOST_SLC_APBWIN_RDATA
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC_APBWIN_RDATA :
bits : 0 - 31 (32 bit)
HOST_SLCHOST_RDCLR0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_SLC0_BIT7_CLRADDR :
bits : 0 - 8 (9 bit)
HOST_SLCHOST_SLC0_BIT6_CLRADDR :
bits : 9 - 17 (9 bit)
HOST_SLCHOST_RDCLR1
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_SLC1_BIT7_CLRADDR :
bits : 0 - 8 (9 bit)
HOST_SLCHOST_SLC1_BIT6_CLRADDR :
bits : 9 - 17 (9 bit)
HOST_SLC0HOST_INT_ENA1
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_TOHOST_BIT0_INT_ENA1 :
bits : 0 - 0 (1 bit)
HOST_SLC0_TOHOST_BIT1_INT_ENA1 :
bits : 1 - 1 (1 bit)
HOST_SLC0_TOHOST_BIT2_INT_ENA1 :
bits : 2 - 2 (1 bit)
HOST_SLC0_TOHOST_BIT3_INT_ENA1 :
bits : 3 - 3 (1 bit)
HOST_SLC0_TOHOST_BIT4_INT_ENA1 :
bits : 4 - 4 (1 bit)
HOST_SLC0_TOHOST_BIT5_INT_ENA1 :
bits : 5 - 5 (1 bit)
HOST_SLC0_TOHOST_BIT6_INT_ENA1 :
bits : 6 - 6 (1 bit)
HOST_SLC0_TOHOST_BIT7_INT_ENA1 :
bits : 7 - 7 (1 bit)
HOST_SLC0_TOKEN0_1TO0_INT_ENA1 :
bits : 8 - 8 (1 bit)
HOST_SLC0_TOKEN1_1TO0_INT_ENA1 :
bits : 9 - 9 (1 bit)
HOST_SLC0_TOKEN0_0TO1_INT_ENA1 :
bits : 10 - 10 (1 bit)
HOST_SLC0_TOKEN1_0TO1_INT_ENA1 :
bits : 11 - 11 (1 bit)
HOST_SLC0HOST_RX_SOF_INT_ENA1 :
bits : 12 - 12 (1 bit)
HOST_SLC0HOST_RX_EOF_INT_ENA1 :
bits : 13 - 13 (1 bit)
HOST_SLC0HOST_RX_START_INT_ENA1 :
bits : 14 - 14 (1 bit)
HOST_SLC0HOST_TX_START_INT_ENA1 :
bits : 15 - 15 (1 bit)
HOST_SLC0_RX_UDF_INT_ENA1 :
bits : 16 - 16 (1 bit)
HOST_SLC0_TX_OVF_INT_ENA1 :
bits : 17 - 17 (1 bit)
HOST_SLC0_RX_PF_VALID_INT_ENA1 :
bits : 18 - 18 (1 bit)
HOST_SLC0_EXT_BIT0_INT_ENA1 :
bits : 19 - 19 (1 bit)
HOST_SLC0_EXT_BIT1_INT_ENA1 :
bits : 20 - 20 (1 bit)
HOST_SLC0_EXT_BIT2_INT_ENA1 :
bits : 21 - 21 (1 bit)
HOST_SLC0_EXT_BIT3_INT_ENA1 :
bits : 22 - 22 (1 bit)
HOST_SLC0_RX_NEW_PACKET_INT_ENA1 :
bits : 23 - 23 (1 bit)
HOST_SLC0_HOST_RD_RETRY_INT_ENA1 :
bits : 24 - 24 (1 bit)
HOST_GPIO_SDIO_INT_ENA1 :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_INT_ENA1
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_TOHOST_BIT0_INT_ENA1 :
bits : 0 - 0 (1 bit)
HOST_SLC1_TOHOST_BIT1_INT_ENA1 :
bits : 1 - 1 (1 bit)
HOST_SLC1_TOHOST_BIT2_INT_ENA1 :
bits : 2 - 2 (1 bit)
HOST_SLC1_TOHOST_BIT3_INT_ENA1 :
bits : 3 - 3 (1 bit)
HOST_SLC1_TOHOST_BIT4_INT_ENA1 :
bits : 4 - 4 (1 bit)
HOST_SLC1_TOHOST_BIT5_INT_ENA1 :
bits : 5 - 5 (1 bit)
HOST_SLC1_TOHOST_BIT6_INT_ENA1 :
bits : 6 - 6 (1 bit)
HOST_SLC1_TOHOST_BIT7_INT_ENA1 :
bits : 7 - 7 (1 bit)
HOST_SLC1_TOKEN0_1TO0_INT_ENA1 :
bits : 8 - 8 (1 bit)
HOST_SLC1_TOKEN1_1TO0_INT_ENA1 :
bits : 9 - 9 (1 bit)
HOST_SLC1_TOKEN0_0TO1_INT_ENA1 :
bits : 10 - 10 (1 bit)
HOST_SLC1_TOKEN1_0TO1_INT_ENA1 :
bits : 11 - 11 (1 bit)
HOST_SLC1HOST_RX_SOF_INT_ENA1 :
bits : 12 - 12 (1 bit)
HOST_SLC1HOST_RX_EOF_INT_ENA1 :
bits : 13 - 13 (1 bit)
HOST_SLC1HOST_RX_START_INT_ENA1 :
bits : 14 - 14 (1 bit)
HOST_SLC1HOST_TX_START_INT_ENA1 :
bits : 15 - 15 (1 bit)
HOST_SLC1_RX_UDF_INT_ENA1 :
bits : 16 - 16 (1 bit)
HOST_SLC1_TX_OVF_INT_ENA1 :
bits : 17 - 17 (1 bit)
HOST_SLC1_RX_PF_VALID_INT_ENA1 :
bits : 18 - 18 (1 bit)
HOST_SLC1_EXT_BIT0_INT_ENA1 :
bits : 19 - 19 (1 bit)
HOST_SLC1_EXT_BIT1_INT_ENA1 :
bits : 20 - 20 (1 bit)
HOST_SLC1_EXT_BIT2_INT_ENA1 :
bits : 21 - 21 (1 bit)
HOST_SLC1_EXT_BIT3_INT_ENA1 :
bits : 22 - 22 (1 bit)
HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 :
bits : 23 - 23 (1 bit)
HOST_SLC1_HOST_RD_RETRY_INT_ENA1 :
bits : 24 - 24 (1 bit)
HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 :
bits : 25 - 25 (1 bit)
HOST_SLCHOST_FUNC2_1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC_FUNC2_INT_EN :
bits : 0 - 0 (1 bit)
HOST_SLCHOSTDATE
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_DATE :
bits : 0 - 31 (32 bit)
HOST_SLCHOSTID
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_ID :
bits : 0 - 31 (32 bit)
HOST_SLCHOST_CONF
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_FRC_SDIO11 :
bits : 0 - 4 (5 bit)
HOST_FRC_SDIO20 :
bits : 5 - 9 (5 bit)
HOST_FRC_NEG_SAMP :
bits : 10 - 14 (5 bit)
HOST_FRC_POS_SAMP :
bits : 15 - 19 (5 bit)
HOST_FRC_QUICK_IN :
bits : 20 - 24 (5 bit)
HOST_SDIO20_INT_DELAY :
bits : 25 - 25 (1 bit)
HOST_SDIO_PAD_PULLUP :
bits : 26 - 26 (1 bit)
HOST_HSPEED_CON_EN :
bits : 27 - 27 (1 bit)
HOST_SLCHOST_INF_ST
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SDIO20_MODE :
bits : 0 - 4 (5 bit)
HOST_SDIO_NEG_SAMP :
bits : 5 - 9 (5 bit)
HOST_SDIO_QUICK_IN :
bits : 10 - 14 (5 bit)
HOST_SLCHOST_FUNC2_2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC_FUNC1_MDSTAT :
bits : 0 - 0 (1 bit)
HOST_SLCHOST_GPIO_STATUS0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_GPIO_SDIO_INT0 :
bits : 0 - 31 (32 bit)
HOST_SLCHOST_GPIO_STATUS1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_GPIO_SDIO_INT1 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_GPIO_IN0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_GPIO_SDIO_IN0 :
bits : 0 - 31 (32 bit)
HOST_SLCHOST_GPIO_IN1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_GPIO_SDIO_IN1 :
bits : 0 - 7 (8 bit)
HOST_SLC0HOST_TOKEN_RDATA
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_TOKEN0 :
bits : 0 - 11 (12 bit)
HOST_SLC0_RX_PF_VALID :
bits : 12 - 12 (1 bit)
HOST_HOSTSLC0_TOKEN1 :
bits : 16 - 27 (12 bit)
HOST_SLC0_RX_PF_EOF :
bits : 28 - 31 (4 bit)
HOST_SLC0_HOST_PF
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_PF_DATA :
bits : 0 - 31 (32 bit)
HOST_SLC1_HOST_PF
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_PF_DATA :
bits : 0 - 31 (32 bit)
HOST_SLC0HOST_INT_RAW
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_TOHOST_BIT0_INT_RAW :
bits : 0 - 0 (1 bit)
HOST_SLC0_TOHOST_BIT1_INT_RAW :
bits : 1 - 1 (1 bit)
HOST_SLC0_TOHOST_BIT2_INT_RAW :
bits : 2 - 2 (1 bit)
HOST_SLC0_TOHOST_BIT3_INT_RAW :
bits : 3 - 3 (1 bit)
HOST_SLC0_TOHOST_BIT4_INT_RAW :
bits : 4 - 4 (1 bit)
HOST_SLC0_TOHOST_BIT5_INT_RAW :
bits : 5 - 5 (1 bit)
HOST_SLC0_TOHOST_BIT6_INT_RAW :
bits : 6 - 6 (1 bit)
HOST_SLC0_TOHOST_BIT7_INT_RAW :
bits : 7 - 7 (1 bit)
HOST_SLC0_TOKEN0_1TO0_INT_RAW :
bits : 8 - 8 (1 bit)
HOST_SLC0_TOKEN1_1TO0_INT_RAW :
bits : 9 - 9 (1 bit)
HOST_SLC0_TOKEN0_0TO1_INT_RAW :
bits : 10 - 10 (1 bit)
HOST_SLC0_TOKEN1_0TO1_INT_RAW :
bits : 11 - 11 (1 bit)
HOST_SLC0HOST_RX_SOF_INT_RAW :
bits : 12 - 12 (1 bit)
HOST_SLC0HOST_RX_EOF_INT_RAW :
bits : 13 - 13 (1 bit)
HOST_SLC0HOST_RX_START_INT_RAW :
bits : 14 - 14 (1 bit)
HOST_SLC0HOST_TX_START_INT_RAW :
bits : 15 - 15 (1 bit)
HOST_SLC0_RX_UDF_INT_RAW :
bits : 16 - 16 (1 bit)
HOST_SLC0_TX_OVF_INT_RAW :
bits : 17 - 17 (1 bit)
HOST_SLC0_RX_PF_VALID_INT_RAW :
bits : 18 - 18 (1 bit)
HOST_SLC0_EXT_BIT0_INT_RAW :
bits : 19 - 19 (1 bit)
HOST_SLC0_EXT_BIT1_INT_RAW :
bits : 20 - 20 (1 bit)
HOST_SLC0_EXT_BIT2_INT_RAW :
bits : 21 - 21 (1 bit)
HOST_SLC0_EXT_BIT3_INT_RAW :
bits : 22 - 22 (1 bit)
HOST_SLC0_RX_NEW_PACKET_INT_RAW :
bits : 23 - 23 (1 bit)
HOST_SLC0_HOST_RD_RETRY_INT_RAW :
bits : 24 - 24 (1 bit)
HOST_GPIO_SDIO_INT_RAW :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_INT_RAW
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_TOHOST_BIT0_INT_RAW :
bits : 0 - 0 (1 bit)
HOST_SLC1_TOHOST_BIT1_INT_RAW :
bits : 1 - 1 (1 bit)
HOST_SLC1_TOHOST_BIT2_INT_RAW :
bits : 2 - 2 (1 bit)
HOST_SLC1_TOHOST_BIT3_INT_RAW :
bits : 3 - 3 (1 bit)
HOST_SLC1_TOHOST_BIT4_INT_RAW :
bits : 4 - 4 (1 bit)
HOST_SLC1_TOHOST_BIT5_INT_RAW :
bits : 5 - 5 (1 bit)
HOST_SLC1_TOHOST_BIT6_INT_RAW :
bits : 6 - 6 (1 bit)
HOST_SLC1_TOHOST_BIT7_INT_RAW :
bits : 7 - 7 (1 bit)
HOST_SLC1_TOKEN0_1TO0_INT_RAW :
bits : 8 - 8 (1 bit)
HOST_SLC1_TOKEN1_1TO0_INT_RAW :
bits : 9 - 9 (1 bit)
HOST_SLC1_TOKEN0_0TO1_INT_RAW :
bits : 10 - 10 (1 bit)
HOST_SLC1_TOKEN1_0TO1_INT_RAW :
bits : 11 - 11 (1 bit)
HOST_SLC1HOST_RX_SOF_INT_RAW :
bits : 12 - 12 (1 bit)
HOST_SLC1HOST_RX_EOF_INT_RAW :
bits : 13 - 13 (1 bit)
HOST_SLC1HOST_RX_START_INT_RAW :
bits : 14 - 14 (1 bit)
HOST_SLC1HOST_TX_START_INT_RAW :
bits : 15 - 15 (1 bit)
HOST_SLC1_RX_UDF_INT_RAW :
bits : 16 - 16 (1 bit)
HOST_SLC1_TX_OVF_INT_RAW :
bits : 17 - 17 (1 bit)
HOST_SLC1_RX_PF_VALID_INT_RAW :
bits : 18 - 18 (1 bit)
HOST_SLC1_EXT_BIT0_INT_RAW :
bits : 19 - 19 (1 bit)
HOST_SLC1_EXT_BIT1_INT_RAW :
bits : 20 - 20 (1 bit)
HOST_SLC1_EXT_BIT2_INT_RAW :
bits : 21 - 21 (1 bit)
HOST_SLC1_EXT_BIT3_INT_RAW :
bits : 22 - 22 (1 bit)
HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW :
bits : 23 - 23 (1 bit)
HOST_SLC1_HOST_RD_RETRY_INT_RAW :
bits : 24 - 24 (1 bit)
HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW :
bits : 25 - 25 (1 bit)
HOST_SLC0HOST_INT_ST
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_TOHOST_BIT0_INT_ST :
bits : 0 - 0 (1 bit)
HOST_SLC0_TOHOST_BIT1_INT_ST :
bits : 1 - 1 (1 bit)
HOST_SLC0_TOHOST_BIT2_INT_ST :
bits : 2 - 2 (1 bit)
HOST_SLC0_TOHOST_BIT3_INT_ST :
bits : 3 - 3 (1 bit)
HOST_SLC0_TOHOST_BIT4_INT_ST :
bits : 4 - 4 (1 bit)
HOST_SLC0_TOHOST_BIT5_INT_ST :
bits : 5 - 5 (1 bit)
HOST_SLC0_TOHOST_BIT6_INT_ST :
bits : 6 - 6 (1 bit)
HOST_SLC0_TOHOST_BIT7_INT_ST :
bits : 7 - 7 (1 bit)
HOST_SLC0_TOKEN0_1TO0_INT_ST :
bits : 8 - 8 (1 bit)
HOST_SLC0_TOKEN1_1TO0_INT_ST :
bits : 9 - 9 (1 bit)
HOST_SLC0_TOKEN0_0TO1_INT_ST :
bits : 10 - 10 (1 bit)
HOST_SLC0_TOKEN1_0TO1_INT_ST :
bits : 11 - 11 (1 bit)
HOST_SLC0HOST_RX_SOF_INT_ST :
bits : 12 - 12 (1 bit)
HOST_SLC0HOST_RX_EOF_INT_ST :
bits : 13 - 13 (1 bit)
HOST_SLC0HOST_RX_START_INT_ST :
bits : 14 - 14 (1 bit)
HOST_SLC0HOST_TX_START_INT_ST :
bits : 15 - 15 (1 bit)
HOST_SLC0_RX_UDF_INT_ST :
bits : 16 - 16 (1 bit)
HOST_SLC0_TX_OVF_INT_ST :
bits : 17 - 17 (1 bit)
HOST_SLC0_RX_PF_VALID_INT_ST :
bits : 18 - 18 (1 bit)
HOST_SLC0_EXT_BIT0_INT_ST :
bits : 19 - 19 (1 bit)
HOST_SLC0_EXT_BIT1_INT_ST :
bits : 20 - 20 (1 bit)
HOST_SLC0_EXT_BIT2_INT_ST :
bits : 21 - 21 (1 bit)
HOST_SLC0_EXT_BIT3_INT_ST :
bits : 22 - 22 (1 bit)
HOST_SLC0_RX_NEW_PACKET_INT_ST :
bits : 23 - 23 (1 bit)
HOST_SLC0_HOST_RD_RETRY_INT_ST :
bits : 24 - 24 (1 bit)
HOST_GPIO_SDIO_INT_ST :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_INT_ST
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_TOHOST_BIT0_INT_ST :
bits : 0 - 0 (1 bit)
HOST_SLC1_TOHOST_BIT1_INT_ST :
bits : 1 - 1 (1 bit)
HOST_SLC1_TOHOST_BIT2_INT_ST :
bits : 2 - 2 (1 bit)
HOST_SLC1_TOHOST_BIT3_INT_ST :
bits : 3 - 3 (1 bit)
HOST_SLC1_TOHOST_BIT4_INT_ST :
bits : 4 - 4 (1 bit)
HOST_SLC1_TOHOST_BIT5_INT_ST :
bits : 5 - 5 (1 bit)
HOST_SLC1_TOHOST_BIT6_INT_ST :
bits : 6 - 6 (1 bit)
HOST_SLC1_TOHOST_BIT7_INT_ST :
bits : 7 - 7 (1 bit)
HOST_SLC1_TOKEN0_1TO0_INT_ST :
bits : 8 - 8 (1 bit)
HOST_SLC1_TOKEN1_1TO0_INT_ST :
bits : 9 - 9 (1 bit)
HOST_SLC1_TOKEN0_0TO1_INT_ST :
bits : 10 - 10 (1 bit)
HOST_SLC1_TOKEN1_0TO1_INT_ST :
bits : 11 - 11 (1 bit)
HOST_SLC1HOST_RX_SOF_INT_ST :
bits : 12 - 12 (1 bit)
HOST_SLC1HOST_RX_EOF_INT_ST :
bits : 13 - 13 (1 bit)
HOST_SLC1HOST_RX_START_INT_ST :
bits : 14 - 14 (1 bit)
HOST_SLC1HOST_TX_START_INT_ST :
bits : 15 - 15 (1 bit)
HOST_SLC1_RX_UDF_INT_ST :
bits : 16 - 16 (1 bit)
HOST_SLC1_TX_OVF_INT_ST :
bits : 17 - 17 (1 bit)
HOST_SLC1_RX_PF_VALID_INT_ST :
bits : 18 - 18 (1 bit)
HOST_SLC1_EXT_BIT0_INT_ST :
bits : 19 - 19 (1 bit)
HOST_SLC1_EXT_BIT1_INT_ST :
bits : 20 - 20 (1 bit)
HOST_SLC1_EXT_BIT2_INT_ST :
bits : 21 - 21 (1 bit)
HOST_SLC1_EXT_BIT3_INT_ST :
bits : 22 - 22 (1 bit)
HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST :
bits : 23 - 23 (1 bit)
HOST_SLC1_HOST_RD_RETRY_INT_ST :
bits : 24 - 24 (1 bit)
HOST_SLC1_BT_RX_NEW_PACKET_INT_ST :
bits : 25 - 25 (1 bit)
HOST_SLCHOST_PKT_LEN
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_HOSTSLC0_LEN :
bits : 0 - 19 (20 bit)
HOST_HOSTSLC0_LEN_CHECK :
bits : 20 - 31 (12 bit)
HOST_SLCHOST_STATE_W0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_STATE0 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_STATE1 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_STATE2 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_STATE3 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_STATE_W1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_STATE4 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_STATE5 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_STATE6 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_STATE7 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W0
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF0 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF1 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF2 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF3 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF4 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF5 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF6 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF7 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF8 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF9 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF10 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF11 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W3
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF12 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF13 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF14 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF15 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W4
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF16 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF17 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF18 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF19 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W5
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF20 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF21 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF22 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF23 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W6
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF24 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF25 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF26 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF27 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W7
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF28 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF29 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF30 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF31 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_PKT_LEN0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_HOSTSLC0_LEN0 :
bits : 0 - 19 (20 bit)
HOST_SLCHOST_PKT_LEN1
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_HOSTSLC0_LEN1 :
bits : 0 - 19 (20 bit)
HOST_SLCHOST_PKT_LEN2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_HOSTSLC0_LEN2 :
bits : 0 - 19 (20 bit)
HOST_SLCHOST_CONF_W8
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF32 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF33 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF34 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF35 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W9
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF36 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF37 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF38 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF39 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W10
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF40 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF41 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF42 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF43 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W11
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF44 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF45 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF46 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF47 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W12
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF48 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF49 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF50 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF51 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W13
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF52 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF53 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF54 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF55 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W14
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF56 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF57 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF58 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF59 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CONF_W15
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CONF60 :
bits : 0 - 7 (8 bit)
HOST_SLCHOST_CONF61 :
bits : 8 - 15 (8 bit)
HOST_SLCHOST_CONF62 :
bits : 16 - 23 (8 bit)
HOST_SLCHOST_CONF63 :
bits : 24 - 31 (8 bit)
HOST_SLCHOST_CHECK_SUM0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CHECK_SUM0 :
bits : 0 - 31 (32 bit)
HOST_SLCHOST_CHECK_SUM1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLCHOST_CHECK_SUM1 :
bits : 0 - 31 (32 bit)
HOST_SLC1HOST_TOKEN_RDATA
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_TOKEN0 :
bits : 0 - 11 (12 bit)
HOST_SLC1_RX_PF_VALID :
bits : 12 - 12 (1 bit)
HOST_HOSTSLC1_TOKEN1 :
bits : 16 - 27 (12 bit)
HOST_SLC1_RX_PF_EOF :
bits : 28 - 31 (4 bit)
HOST_SLC0HOST_TOKEN_WDATA
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0HOST_TOKEN0_WD :
bits : 0 - 11 (12 bit)
HOST_SLC0HOST_TOKEN1_WD :
bits : 16 - 27 (12 bit)
HOST_SLC1HOST_TOKEN_WDATA
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1HOST_TOKEN0_WD :
bits : 0 - 11 (12 bit)
HOST_SLC1HOST_TOKEN1_WD :
bits : 16 - 27 (12 bit)
HOST_SLCHOST_TOKEN_CON
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0HOST_TOKEN0_DEC :
bits : 0 - 0 (1 bit)
HOST_SLC0HOST_TOKEN1_DEC :
bits : 1 - 1 (1 bit)
HOST_SLC0HOST_TOKEN0_WR :
bits : 2 - 2 (1 bit)
HOST_SLC0HOST_TOKEN1_WR :
bits : 3 - 3 (1 bit)
HOST_SLC1HOST_TOKEN0_DEC :
bits : 4 - 4 (1 bit)
HOST_SLC1HOST_TOKEN1_DEC :
bits : 5 - 5 (1 bit)
HOST_SLC1HOST_TOKEN0_WR :
bits : 6 - 6 (1 bit)
HOST_SLC1HOST_TOKEN1_WR :
bits : 7 - 7 (1 bit)
HOST_SLC0HOST_LEN_WR :
bits : 8 - 8 (1 bit)
HOST_SLC0HOST_INT_CLR
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_TOHOST_BIT0_INT_CLR :
bits : 0 - 0 (1 bit)
HOST_SLC0_TOHOST_BIT1_INT_CLR :
bits : 1 - 1 (1 bit)
HOST_SLC0_TOHOST_BIT2_INT_CLR :
bits : 2 - 2 (1 bit)
HOST_SLC0_TOHOST_BIT3_INT_CLR :
bits : 3 - 3 (1 bit)
HOST_SLC0_TOHOST_BIT4_INT_CLR :
bits : 4 - 4 (1 bit)
HOST_SLC0_TOHOST_BIT5_INT_CLR :
bits : 5 - 5 (1 bit)
HOST_SLC0_TOHOST_BIT6_INT_CLR :
bits : 6 - 6 (1 bit)
HOST_SLC0_TOHOST_BIT7_INT_CLR :
bits : 7 - 7 (1 bit)
HOST_SLC0_TOKEN0_1TO0_INT_CLR :
bits : 8 - 8 (1 bit)
HOST_SLC0_TOKEN1_1TO0_INT_CLR :
bits : 9 - 9 (1 bit)
HOST_SLC0_TOKEN0_0TO1_INT_CLR :
bits : 10 - 10 (1 bit)
HOST_SLC0_TOKEN1_0TO1_INT_CLR :
bits : 11 - 11 (1 bit)
HOST_SLC0HOST_RX_SOF_INT_CLR :
bits : 12 - 12 (1 bit)
HOST_SLC0HOST_RX_EOF_INT_CLR :
bits : 13 - 13 (1 bit)
HOST_SLC0HOST_RX_START_INT_CLR :
bits : 14 - 14 (1 bit)
HOST_SLC0HOST_TX_START_INT_CLR :
bits : 15 - 15 (1 bit)
HOST_SLC0_RX_UDF_INT_CLR :
bits : 16 - 16 (1 bit)
HOST_SLC0_TX_OVF_INT_CLR :
bits : 17 - 17 (1 bit)
HOST_SLC0_RX_PF_VALID_INT_CLR :
bits : 18 - 18 (1 bit)
HOST_SLC0_EXT_BIT0_INT_CLR :
bits : 19 - 19 (1 bit)
HOST_SLC0_EXT_BIT1_INT_CLR :
bits : 20 - 20 (1 bit)
HOST_SLC0_EXT_BIT2_INT_CLR :
bits : 21 - 21 (1 bit)
HOST_SLC0_EXT_BIT3_INT_CLR :
bits : 22 - 22 (1 bit)
HOST_SLC0_RX_NEW_PACKET_INT_CLR :
bits : 23 - 23 (1 bit)
HOST_SLC0_HOST_RD_RETRY_INT_CLR :
bits : 24 - 24 (1 bit)
HOST_GPIO_SDIO_INT_CLR :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_INT_CLR
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_TOHOST_BIT0_INT_CLR :
bits : 0 - 0 (1 bit)
HOST_SLC1_TOHOST_BIT1_INT_CLR :
bits : 1 - 1 (1 bit)
HOST_SLC1_TOHOST_BIT2_INT_CLR :
bits : 2 - 2 (1 bit)
HOST_SLC1_TOHOST_BIT3_INT_CLR :
bits : 3 - 3 (1 bit)
HOST_SLC1_TOHOST_BIT4_INT_CLR :
bits : 4 - 4 (1 bit)
HOST_SLC1_TOHOST_BIT5_INT_CLR :
bits : 5 - 5 (1 bit)
HOST_SLC1_TOHOST_BIT6_INT_CLR :
bits : 6 - 6 (1 bit)
HOST_SLC1_TOHOST_BIT7_INT_CLR :
bits : 7 - 7 (1 bit)
HOST_SLC1_TOKEN0_1TO0_INT_CLR :
bits : 8 - 8 (1 bit)
HOST_SLC1_TOKEN1_1TO0_INT_CLR :
bits : 9 - 9 (1 bit)
HOST_SLC1_TOKEN0_0TO1_INT_CLR :
bits : 10 - 10 (1 bit)
HOST_SLC1_TOKEN1_0TO1_INT_CLR :
bits : 11 - 11 (1 bit)
HOST_SLC1HOST_RX_SOF_INT_CLR :
bits : 12 - 12 (1 bit)
HOST_SLC1HOST_RX_EOF_INT_CLR :
bits : 13 - 13 (1 bit)
HOST_SLC1HOST_RX_START_INT_CLR :
bits : 14 - 14 (1 bit)
HOST_SLC1HOST_TX_START_INT_CLR :
bits : 15 - 15 (1 bit)
HOST_SLC1_RX_UDF_INT_CLR :
bits : 16 - 16 (1 bit)
HOST_SLC1_TX_OVF_INT_CLR :
bits : 17 - 17 (1 bit)
HOST_SLC1_RX_PF_VALID_INT_CLR :
bits : 18 - 18 (1 bit)
HOST_SLC1_EXT_BIT0_INT_CLR :
bits : 19 - 19 (1 bit)
HOST_SLC1_EXT_BIT1_INT_CLR :
bits : 20 - 20 (1 bit)
HOST_SLC1_EXT_BIT2_INT_CLR :
bits : 21 - 21 (1 bit)
HOST_SLC1_EXT_BIT3_INT_CLR :
bits : 22 - 22 (1 bit)
HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR :
bits : 23 - 23 (1 bit)
HOST_SLC1_HOST_RD_RETRY_INT_CLR :
bits : 24 - 24 (1 bit)
HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR :
bits : 25 - 25 (1 bit)
HOST_SLC0HOST_FUNC1_INT_ENA
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA :
bits : 8 - 8 (1 bit)
HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA :
bits : 9 - 9 (1 bit)
HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA :
bits : 10 - 10 (1 bit)
HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA :
bits : 11 - 11 (1 bit)
HOST_FN1_SLC0HOST_RX_SOF_INT_ENA :
bits : 12 - 12 (1 bit)
HOST_FN1_SLC0HOST_RX_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
HOST_FN1_SLC0HOST_RX_START_INT_ENA :
bits : 14 - 14 (1 bit)
HOST_FN1_SLC0HOST_TX_START_INT_ENA :
bits : 15 - 15 (1 bit)
HOST_FN1_SLC0_RX_UDF_INT_ENA :
bits : 16 - 16 (1 bit)
HOST_FN1_SLC0_TX_OVF_INT_ENA :
bits : 17 - 17 (1 bit)
HOST_FN1_SLC0_RX_PF_VALID_INT_ENA :
bits : 18 - 18 (1 bit)
HOST_FN1_SLC0_EXT_BIT0_INT_ENA :
bits : 19 - 19 (1 bit)
HOST_FN1_SLC0_EXT_BIT1_INT_ENA :
bits : 20 - 20 (1 bit)
HOST_FN1_SLC0_EXT_BIT2_INT_ENA :
bits : 21 - 21 (1 bit)
HOST_FN1_SLC0_EXT_BIT3_INT_ENA :
bits : 22 - 22 (1 bit)
HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA :
bits : 23 - 23 (1 bit)
HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA :
bits : 24 - 24 (1 bit)
HOST_FN1_GPIO_SDIO_INT_ENA :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_FUNC1_INT_ENA
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA :
bits : 8 - 8 (1 bit)
HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA :
bits : 9 - 9 (1 bit)
HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA :
bits : 10 - 10 (1 bit)
HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA :
bits : 11 - 11 (1 bit)
HOST_FN1_SLC1HOST_RX_SOF_INT_ENA :
bits : 12 - 12 (1 bit)
HOST_FN1_SLC1HOST_RX_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
HOST_FN1_SLC1HOST_RX_START_INT_ENA :
bits : 14 - 14 (1 bit)
HOST_FN1_SLC1HOST_TX_START_INT_ENA :
bits : 15 - 15 (1 bit)
HOST_FN1_SLC1_RX_UDF_INT_ENA :
bits : 16 - 16 (1 bit)
HOST_FN1_SLC1_TX_OVF_INT_ENA :
bits : 17 - 17 (1 bit)
HOST_FN1_SLC1_RX_PF_VALID_INT_ENA :
bits : 18 - 18 (1 bit)
HOST_FN1_SLC1_EXT_BIT0_INT_ENA :
bits : 19 - 19 (1 bit)
HOST_FN1_SLC1_EXT_BIT1_INT_ENA :
bits : 20 - 20 (1 bit)
HOST_FN1_SLC1_EXT_BIT2_INT_ENA :
bits : 21 - 21 (1 bit)
HOST_FN1_SLC1_EXT_BIT3_INT_ENA :
bits : 22 - 22 (1 bit)
HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA :
bits : 23 - 23 (1 bit)
HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA :
bits : 24 - 24 (1 bit)
HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA :
bits : 25 - 25 (1 bit)
HOST_SLC0HOST_FUNC2_INT_ENA
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA :
bits : 8 - 8 (1 bit)
HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA :
bits : 9 - 9 (1 bit)
HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA :
bits : 10 - 10 (1 bit)
HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA :
bits : 11 - 11 (1 bit)
HOST_FN2_SLC0HOST_RX_SOF_INT_ENA :
bits : 12 - 12 (1 bit)
HOST_FN2_SLC0HOST_RX_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
HOST_FN2_SLC0HOST_RX_START_INT_ENA :
bits : 14 - 14 (1 bit)
HOST_FN2_SLC0HOST_TX_START_INT_ENA :
bits : 15 - 15 (1 bit)
HOST_FN2_SLC0_RX_UDF_INT_ENA :
bits : 16 - 16 (1 bit)
HOST_FN2_SLC0_TX_OVF_INT_ENA :
bits : 17 - 17 (1 bit)
HOST_FN2_SLC0_RX_PF_VALID_INT_ENA :
bits : 18 - 18 (1 bit)
HOST_FN2_SLC0_EXT_BIT0_INT_ENA :
bits : 19 - 19 (1 bit)
HOST_FN2_SLC0_EXT_BIT1_INT_ENA :
bits : 20 - 20 (1 bit)
HOST_FN2_SLC0_EXT_BIT2_INT_ENA :
bits : 21 - 21 (1 bit)
HOST_FN2_SLC0_EXT_BIT3_INT_ENA :
bits : 22 - 22 (1 bit)
HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA :
bits : 23 - 23 (1 bit)
HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA :
bits : 24 - 24 (1 bit)
HOST_FN2_GPIO_SDIO_INT_ENA :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_FUNC2_INT_ENA
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA :
bits : 8 - 8 (1 bit)
HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA :
bits : 9 - 9 (1 bit)
HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA :
bits : 10 - 10 (1 bit)
HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA :
bits : 11 - 11 (1 bit)
HOST_FN2_SLC1HOST_RX_SOF_INT_ENA :
bits : 12 - 12 (1 bit)
HOST_FN2_SLC1HOST_RX_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
HOST_FN2_SLC1HOST_RX_START_INT_ENA :
bits : 14 - 14 (1 bit)
HOST_FN2_SLC1HOST_TX_START_INT_ENA :
bits : 15 - 15 (1 bit)
HOST_FN2_SLC1_RX_UDF_INT_ENA :
bits : 16 - 16 (1 bit)
HOST_FN2_SLC1_TX_OVF_INT_ENA :
bits : 17 - 17 (1 bit)
HOST_FN2_SLC1_RX_PF_VALID_INT_ENA :
bits : 18 - 18 (1 bit)
HOST_FN2_SLC1_EXT_BIT0_INT_ENA :
bits : 19 - 19 (1 bit)
HOST_FN2_SLC1_EXT_BIT1_INT_ENA :
bits : 20 - 20 (1 bit)
HOST_FN2_SLC1_EXT_BIT2_INT_ENA :
bits : 21 - 21 (1 bit)
HOST_FN2_SLC1_EXT_BIT3_INT_ENA :
bits : 22 - 22 (1 bit)
HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA :
bits : 23 - 23 (1 bit)
HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA :
bits : 24 - 24 (1 bit)
HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA :
bits : 25 - 25 (1 bit)
HOST_SLC0HOST_INT_ENA
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0_TOHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
HOST_SLC0_TOHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
HOST_SLC0_TOHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
HOST_SLC0_TOHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
HOST_SLC0_TOHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
HOST_SLC0_TOHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
HOST_SLC0_TOHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
HOST_SLC0_TOHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
HOST_SLC0_TOKEN0_1TO0_INT_ENA :
bits : 8 - 8 (1 bit)
HOST_SLC0_TOKEN1_1TO0_INT_ENA :
bits : 9 - 9 (1 bit)
HOST_SLC0_TOKEN0_0TO1_INT_ENA :
bits : 10 - 10 (1 bit)
HOST_SLC0_TOKEN1_0TO1_INT_ENA :
bits : 11 - 11 (1 bit)
HOST_SLC0HOST_RX_SOF_INT_ENA :
bits : 12 - 12 (1 bit)
HOST_SLC0HOST_RX_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
HOST_SLC0HOST_RX_START_INT_ENA :
bits : 14 - 14 (1 bit)
HOST_SLC0HOST_TX_START_INT_ENA :
bits : 15 - 15 (1 bit)
HOST_SLC0_RX_UDF_INT_ENA :
bits : 16 - 16 (1 bit)
HOST_SLC0_TX_OVF_INT_ENA :
bits : 17 - 17 (1 bit)
HOST_SLC0_RX_PF_VALID_INT_ENA :
bits : 18 - 18 (1 bit)
HOST_SLC0_EXT_BIT0_INT_ENA :
bits : 19 - 19 (1 bit)
HOST_SLC0_EXT_BIT1_INT_ENA :
bits : 20 - 20 (1 bit)
HOST_SLC0_EXT_BIT2_INT_ENA :
bits : 21 - 21 (1 bit)
HOST_SLC0_EXT_BIT3_INT_ENA :
bits : 22 - 22 (1 bit)
HOST_SLC0_RX_NEW_PACKET_INT_ENA :
bits : 23 - 23 (1 bit)
HOST_SLC0_HOST_RD_RETRY_INT_ENA :
bits : 24 - 24 (1 bit)
HOST_GPIO_SDIO_INT_ENA :
bits : 25 - 25 (1 bit)
HOST_SLC1HOST_INT_ENA
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1_TOHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
HOST_SLC1_TOHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
HOST_SLC1_TOHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
HOST_SLC1_TOHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
HOST_SLC1_TOHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
HOST_SLC1_TOHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
HOST_SLC1_TOHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
HOST_SLC1_TOHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
HOST_SLC1_TOKEN0_1TO0_INT_ENA :
bits : 8 - 8 (1 bit)
HOST_SLC1_TOKEN1_1TO0_INT_ENA :
bits : 9 - 9 (1 bit)
HOST_SLC1_TOKEN0_0TO1_INT_ENA :
bits : 10 - 10 (1 bit)
HOST_SLC1_TOKEN1_0TO1_INT_ENA :
bits : 11 - 11 (1 bit)
HOST_SLC1HOST_RX_SOF_INT_ENA :
bits : 12 - 12 (1 bit)
HOST_SLC1HOST_RX_EOF_INT_ENA :
bits : 13 - 13 (1 bit)
HOST_SLC1HOST_RX_START_INT_ENA :
bits : 14 - 14 (1 bit)
HOST_SLC1HOST_TX_START_INT_ENA :
bits : 15 - 15 (1 bit)
HOST_SLC1_RX_UDF_INT_ENA :
bits : 16 - 16 (1 bit)
HOST_SLC1_TX_OVF_INT_ENA :
bits : 17 - 17 (1 bit)
HOST_SLC1_RX_PF_VALID_INT_ENA :
bits : 18 - 18 (1 bit)
HOST_SLC1_EXT_BIT0_INT_ENA :
bits : 19 - 19 (1 bit)
HOST_SLC1_EXT_BIT1_INT_ENA :
bits : 20 - 20 (1 bit)
HOST_SLC1_EXT_BIT2_INT_ENA :
bits : 21 - 21 (1 bit)
HOST_SLC1_EXT_BIT3_INT_ENA :
bits : 22 - 22 (1 bit)
HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA :
bits : 23 - 23 (1 bit)
HOST_SLC1_HOST_RD_RETRY_INT_ENA :
bits : 24 - 24 (1 bit)
HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA :
bits : 25 - 25 (1 bit)
HOST_SLC0HOST_RX_INFOR
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0HOST_RX_INFOR :
bits : 0 - 19 (20 bit)
HOST_SLC1HOST_RX_INFOR
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC1HOST_RX_INFOR :
bits : 0 - 19 (20 bit)
HOST_SLC0HOST_LEN_WD
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST_SLC0HOST_LEN_WD :
bits : 0 - 31 (32 bit)
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