\n
address_offset : 0x0 Bytes (0x0)
size : 0x540 byte (0x0)
mem_usage : registers
protection : not protected
SENS_SAR_READ_CTRL
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR1_CLK_DIV :
bits : 0 - 7 (8 bit)
SAR1_SAMPLE_CYCLE :
bits : 8 - 15 (8 bit)
SAR1_SAMPLE_BIT :
bits : 16 - 17 (2 bit)
SAR1_CLK_GATED :
bits : 18 - 18 (1 bit)
SAR1_SAMPLE_NUM :
bits : 19 - 26 (8 bit)
SAR1_DIG_FORCE :
bits : 27 - 27 (1 bit)
SAR1_DATA_INV :
bits : 28 - 28 (1 bit)
SENS_SAR_MEAS_CTRL
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XPD_SAR_AMP_FSM :
bits : 0 - 3 (4 bit)
AMP_RST_FB_FSM :
bits : 4 - 7 (4 bit)
AMP_SHORT_REF_FSM :
bits : 8 - 11 (4 bit)
AMP_SHORT_REF_GND_FSM :
bits : 12 - 15 (4 bit)
XPD_SAR_FSM :
bits : 16 - 19 (4 bit)
SAR_RSTB_FSM :
bits : 20 - 23 (4 bit)
SAR2_XPD_WAIT :
bits : 24 - 31 (8 bit)
SENS_SAR_READ_STATUS2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR2_READER_STATUS :
bits : 0 - 31 (32 bit)
SENS_ULP_CP_SLEEP_CYC0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEP_CYCLES_S0 :
bits : 0 - 31 (32 bit)
SENS_ULP_CP_SLEEP_CYC1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEP_CYCLES_S1 :
bits : 0 - 31 (32 bit)
SENS_ULP_CP_SLEEP_CYC2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEP_CYCLES_S2 :
bits : 0 - 31 (32 bit)
SENS_ULP_CP_SLEEP_CYC3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEP_CYCLES_S3 :
bits : 0 - 31 (32 bit)
SENS_ULP_CP_SLEEP_CYC4
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEP_CYCLES_S4 :
bits : 0 - 31 (32 bit)
SENS_SAR_START_FORCE
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR1_BIT_WIDTH :
bits : 0 - 1 (2 bit)
SAR2_BIT_WIDTH :
bits : 2 - 3 (2 bit)
SAR2_EN_TEST :
bits : 4 - 4 (1 bit)
SAR2_PWDET_CCT :
bits : 5 - 7 (3 bit)
ULP_CP_FORCE_START_TOP :
bits : 8 - 8 (1 bit)
ULP_CP_START_TOP :
bits : 9 - 9 (1 bit)
SARCLK_EN :
bits : 10 - 10 (1 bit)
PC_INIT :
bits : 11 - 21 (11 bit)
SAR2_STOP :
bits : 22 - 22 (1 bit)
SAR1_STOP :
bits : 23 - 23 (1 bit)
SAR2_PWDET_EN :
bits : 24 - 24 (1 bit)
SENS_SAR_MEM_WR_CTRL
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEM_WR_ADDR_INIT :
bits : 0 - 10 (11 bit)
MEM_WR_ADDR_SIZE :
bits : 11 - 21 (11 bit)
RTC_MEM_WR_OFFST_CLR :
bits : 22 - 22 (1 bit)
SENS_SAR_ATTEN1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR1_ATTEN :
bits : 0 - 31 (32 bit)
SENS_SAR_ATTEN2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR2_ATTEN :
bits : 0 - 31 (32 bit)
SENS_SAR_SLAVE_ADDR1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C_SLAVE_ADDR1 :
bits : 0 - 10 (11 bit)
I2C_SLAVE_ADDR0 :
bits : 11 - 21 (11 bit)
MEAS_STATUS :
bits : 22 - 29 (8 bit)
SENS_SAR_READ_STATUS1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR1_READER_STATUS :
bits : 0 - 31 (32 bit)
SENS_SAR_SLAVE_ADDR2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C_SLAVE_ADDR3 :
bits : 0 - 10 (11 bit)
I2C_SLAVE_ADDR2 :
bits : 11 - 21 (11 bit)
SENS_SAR_SLAVE_ADDR3
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C_SLAVE_ADDR5 :
bits : 0 - 10 (11 bit)
I2C_SLAVE_ADDR4 :
bits : 11 - 21 (11 bit)
TSENS_OUT :
bits : 22 - 29 (8 bit)
TSENS_RDY_OUT :
bits : 30 - 30 (1 bit)
SENS_SAR_SLAVE_ADDR4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C_SLAVE_ADDR7 :
bits : 0 - 10 (11 bit)
I2C_SLAVE_ADDR6 :
bits : 11 - 21 (11 bit)
I2C_RDATA :
bits : 22 - 29 (8 bit)
I2C_DONE :
bits : 30 - 30 (1 bit)
SENS_SAR_TSENS_CTRL
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSENS_XPD_WAIT :
bits : 0 - 11 (12 bit)
TSENS_XPD_FORCE :
bits : 12 - 12 (1 bit)
TSENS_CLK_INV :
bits : 13 - 13 (1 bit)
TSENS_CLK_GATED :
bits : 14 - 14 (1 bit)
TSENS_IN_INV :
bits : 15 - 15 (1 bit)
TSENS_CLK_DIV :
bits : 16 - 23 (8 bit)
TSENS_POWER_UP :
bits : 24 - 24 (1 bit)
TSENS_POWER_UP_FORCE :
bits : 25 - 25 (1 bit)
TSENS_DUMP_OUT :
bits : 26 - 26 (1 bit)
SENS_SAR_I2C_CTRL
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_I2C_CTRL :
bits : 0 - 27 (28 bit)
SAR_I2C_START :
bits : 28 - 28 (1 bit)
SAR_I2C_START_FORCE :
bits : 29 - 29 (1 bit)
SENS_SAR_MEAS_START1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEAS1_DATA_SAR :
bits : 0 - 15 (16 bit)
MEAS1_DONE_SAR :
bits : 16 - 16 (1 bit)
MEAS1_START_SAR :
bits : 17 - 17 (1 bit)
MEAS1_START_FORCE :
bits : 18 - 18 (1 bit)
SAR1_EN_PAD :
bits : 19 - 30 (12 bit)
SAR1_EN_PAD_FORCE :
bits : 31 - 31 (1 bit)
SENS_SAR_TOUCH_CTRL1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_DELAY :
bits : 0 - 15 (16 bit)
TOUCH_XPD_WAIT :
bits : 16 - 23 (8 bit)
TOUCH_OUT_SEL :
bits : 24 - 24 (1 bit)
TOUCH_OUT_1EN :
bits : 25 - 25 (1 bit)
XPD_HALL_FORCE :
bits : 26 - 26 (1 bit)
HALL_PHASE_FORCE :
bits : 27 - 27 (1 bit)
SENS_SAR_TOUCH_THRES1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_OUT_TH1 :
bits : 0 - 15 (16 bit)
TOUCH_OUT_TH0 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_THRES2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_OUT_TH3 :
bits : 0 - 15 (16 bit)
TOUCH_OUT_TH2 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_THRES3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_OUT_TH5 :
bits : 0 - 15 (16 bit)
TOUCH_OUT_TH4 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_THRES4
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_OUT_TH7 :
bits : 0 - 15 (16 bit)
TOUCH_OUT_TH6 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_THRES5
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_OUT_TH9 :
bits : 0 - 15 (16 bit)
TOUCH_OUT_TH8 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_OUT1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_OUT1 :
bits : 0 - 15 (16 bit)
TOUCH_MEAS_OUT0 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_OUT2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_OUT3 :
bits : 0 - 15 (16 bit)
TOUCH_MEAS_OUT2 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_OUT3
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_OUT5 :
bits : 0 - 15 (16 bit)
TOUCH_MEAS_OUT4 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_OUT4
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_OUT7 :
bits : 0 - 15 (16 bit)
TOUCH_MEAS_OUT6 :
bits : 16 - 31 (16 bit)
SENS_SAR_MEAS_WAIT1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_AMP_WAIT1 :
bits : 0 - 15 (16 bit)
SAR_AMP_WAIT2 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_OUT5
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_OUT9 :
bits : 0 - 15 (16 bit)
TOUCH_MEAS_OUT8 :
bits : 16 - 31 (16 bit)
SENS_SAR_TOUCH_CTRL2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_MEAS_EN :
bits : 0 - 9 (10 bit)
TOUCH_MEAS_DONE :
bits : 10 - 10 (1 bit)
TOUCH_START_FSM_EN :
bits : 11 - 11 (1 bit)
TOUCH_START_EN :
bits : 12 - 12 (1 bit)
TOUCH_START_FORCE :
bits : 13 - 13 (1 bit)
TOUCH_SLEEP_CYCLES :
bits : 14 - 29 (16 bit)
TOUCH_MEAS_EN_CLR :
bits : 30 - 30 (1 bit)
SENS_SAR_TOUCH_ENABLE
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_PAD_WORKEN :
bits : 0 - 9 (10 bit)
TOUCH_PAD_OUTEN2 :
bits : 10 - 19 (10 bit)
TOUCH_PAD_OUTEN1 :
bits : 20 - 29 (10 bit)
SENS_SAR_READ_CTRL2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR2_CLK_DIV :
bits : 0 - 7 (8 bit)
SAR2_SAMPLE_CYCLE :
bits : 8 - 15 (8 bit)
SAR2_SAMPLE_BIT :
bits : 16 - 17 (2 bit)
SAR2_CLK_GATED :
bits : 18 - 18 (1 bit)
SAR2_SAMPLE_NUM :
bits : 19 - 26 (8 bit)
SAR2_PWDET_FORCE :
bits : 27 - 27 (1 bit)
SAR2_DIG_FORCE :
bits : 28 - 28 (1 bit)
SAR2_DATA_INV :
bits : 29 - 29 (1 bit)
SENS_SAR_MEAS_START2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEAS2_DATA_SAR :
bits : 0 - 15 (16 bit)
MEAS2_DONE_SAR :
bits : 16 - 16 (1 bit)
MEAS2_START_SAR :
bits : 17 - 17 (1 bit)
MEAS2_START_FORCE :
bits : 18 - 18 (1 bit)
SAR2_EN_PAD :
bits : 19 - 30 (12 bit)
SAR2_EN_PAD_FORCE :
bits : 31 - 31 (1 bit)
SENS_SAR_DAC_CTRL1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_FSTEP :
bits : 0 - 15 (16 bit)
SW_TONE_EN :
bits : 16 - 16 (1 bit)
DEBUG_BIT_SEL :
bits : 17 - 21 (5 bit)
DAC_DIG_FORCE :
bits : 22 - 22 (1 bit)
DAC_CLK_FORCE_LOW :
bits : 23 - 23 (1 bit)
DAC_CLK_FORCE_HIGH :
bits : 24 - 24 (1 bit)
DAC_CLK_INV :
bits : 25 - 25 (1 bit)
SENS_SAR_DAC_CTRL2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC_DC1 :
bits : 0 - 7 (8 bit)
DAC_DC2 :
bits : 8 - 15 (8 bit)
DAC_SCALE1 :
bits : 16 - 17 (2 bit)
DAC_SCALE2 :
bits : 18 - 19 (2 bit)
DAC_INV1 :
bits : 20 - 21 (2 bit)
DAC_INV2 :
bits : 22 - 23 (2 bit)
DAC_CW_EN1 :
bits : 24 - 24 (1 bit)
DAC_CW_EN2 :
bits : 25 - 25 (1 bit)
SENS_SAR_MEAS_CTRL2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR1_DAC_XPD_FSM :
bits : 0 - 3 (4 bit)
SAR1_DAC_XPD_FSM_IDLE :
bits : 4 - 4 (1 bit)
XPD_SAR_AMP_FSM_IDLE :
bits : 5 - 5 (1 bit)
AMP_RST_FB_FSM_IDLE :
bits : 6 - 6 (1 bit)
AMP_SHORT_REF_FSM_IDLE :
bits : 7 - 7 (1 bit)
AMP_SHORT_REF_GND_FSM_IDLE :
bits : 8 - 8 (1 bit)
XPD_SAR_FSM_IDLE :
bits : 9 - 9 (1 bit)
SAR_RSTB_FSM_IDLE :
bits : 10 - 10 (1 bit)
SAR2_RSTB_FORCE :
bits : 11 - 12 (2 bit)
AMP_RST_FB_FORCE :
bits : 13 - 14 (2 bit)
AMP_SHORT_REF_FORCE :
bits : 15 - 16 (2 bit)
AMP_SHORT_REF_GND_FORCE :
bits : 17 - 18 (2 bit)
SENS_SAR_MEAS_WAIT2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_AMP_WAIT3 :
bits : 0 - 15 (16 bit)
FORCE_XPD_AMP :
bits : 16 - 17 (2 bit)
FORCE_XPD_SAR :
bits : 18 - 19 (2 bit)
SAR2_RSTB_WAIT :
bits : 20 - 27 (8 bit)
SENS_SAR_NOUSE
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_NOUSE :
bits : 0 - 31 (32 bit)
SENS_SARDATE
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_DATE :
bits : 0 - 27 (28 bit)
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