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RTCIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x660 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OUT

ENABLE_W1TS

PIN4

ENABLE_W1TC

PIN5

STATUS

PIN6

STATUS_W1TS

PIN7

STATUS_W1TC

PIN8

IN

PIN9

PIN10

PIN11

PIN12

PIN13

OUT_W1TS

PIN14

PIN15

PIN16

PIN0

PIN17

RTC_DEBUG_SEL

DIG_PAD_HOLD

HALL_SENS

PIN1

SENSOR_PADS

OUT_W1TC

ADC_PAD

PAD_DAC1

PAD_DAC2

XTAL_32K_PAD

TOUCH_CFG

TOUCH_PAD0

TOUCH_PAD1

TOUCH_PAD2

TOUCH_PAD3

TOUCH_PAD4

TOUCH_PAD5

PIN2

TOUCH_PAD6

TOUCH_PAD7

TOUCH_PAD8

TOUCH_PAD9

EXT_WAKEUP0

ENABLE

XTL_EXT_CTR

SAR_I2C_IO

DATE

PIN3


OUT

RTC_GPIO_OUT
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUT OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_DATA

OUT_DATA :
bits : 14 - 31 (18 bit)


ENABLE_W1TS

RTC_GPIO_ENABLE_W1TS
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE_W1TS ENABLE_W1TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE_W1TS

ENABLE_W1TS :
bits : 14 - 31 (18 bit)


PIN4

RTC_GPIO_PIN0
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN4 PIN4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


ENABLE_W1TC

RTC_GPIO_ENABLE_W1TC
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE_W1TC ENABLE_W1TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE_W1TC

ENABLE_W1TC :
bits : 14 - 31 (18 bit)


PIN5

RTC_GPIO_PIN0
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN5 PIN5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


STATUS

RTC_GPIO_STATUS
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_INT

STATUS_INT :
bits : 14 - 31 (18 bit)


PIN6

RTC_GPIO_PIN0
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN6 PIN6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


STATUS_W1TS

RTC_GPIO_STATUS_W1TS
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_W1TS STATUS_W1TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_INT_W1TS

STATUS_INT_W1TS :
bits : 14 - 31 (18 bit)


PIN7

RTC_GPIO_PIN0
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN7 PIN7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


STATUS_W1TC

RTC_GPIO_STATUS_W1TC
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_W1TC STATUS_W1TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_INT_W1TC

STATUS_INT_W1TC :
bits : 14 - 31 (18 bit)


PIN8

RTC_GPIO_PIN0
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN8 PIN8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


IN

RTC_GPIO_IN
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IN IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IN_NEXT

IN_NEXT :
bits : 14 - 31 (18 bit)


PIN9

RTC_GPIO_PIN0
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN9 PIN9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN10

RTC_GPIO_PIN0
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN10 PIN10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN11

RTC_GPIO_PIN0
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN11 PIN11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN12

RTC_GPIO_PIN0
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN12 PIN12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN13

RTC_GPIO_PIN0
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN13 PIN13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


OUT_W1TS

RTC_GPIO_OUT_W1TS
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUT_W1TS OUT_W1TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_DATA_W1TS

OUT_DATA_W1TS :
bits : 14 - 31 (18 bit)


PIN14

RTC_GPIO_PIN0
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN14 PIN14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN15

RTC_GPIO_PIN0
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN15 PIN15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN16

RTC_GPIO_PIN0
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN16 PIN16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN0

RTC_GPIO_PIN0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN0 PIN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


PIN17

RTC_GPIO_PIN0
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN17 PIN17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


RTC_DEBUG_SEL

RTC_IO_RTC_DEBUG_SEL
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_DEBUG_SEL RTC_DEBUG_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUG_SEL0 DEBUG_SEL1 DEBUG_SEL2 DEBUG_SEL3 DEBUG_SEL4 DEBUG_12M_NO_GATING

DEBUG_SEL0 :
bits : 0 - 4 (5 bit)

DEBUG_SEL1 :
bits : 5 - 9 (5 bit)

DEBUG_SEL2 :
bits : 10 - 14 (5 bit)

DEBUG_SEL3 :
bits : 15 - 19 (5 bit)

DEBUG_SEL4 :
bits : 20 - 24 (5 bit)

DEBUG_12M_NO_GATING :
bits : 25 - 25 (1 bit)


DIG_PAD_HOLD

RTC_IO_DIG_PAD_HOLD
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIG_PAD_HOLD DIG_PAD_HOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIG_PAD_HOLD

DIG_PAD_HOLD :
bits : 0 - 31 (32 bit)


HALL_SENS

RTC_IO_HALL_SENS
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HALL_SENS HALL_SENS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALL_PHASE XPD_HALL

HALL_PHASE :
bits : 30 - 30 (1 bit)

XPD_HALL :
bits : 31 - 31 (1 bit)


PIN1

RTC_GPIO_PIN0
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN1 PIN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


SENSOR_PADS

RTC_IO_SENSOR_PADS
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SENSOR_PADS SENSOR_PADS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SENSE4_FUN_IE SENSE4_SLP_IE SENSE4_SLP_SEL SENSE4_FUN_SEL SENSE3_FUN_IE SENSE3_SLP_IE SENSE3_SLP_SEL SENSE3_FUN_SEL SENSE2_FUN_IE SENSE2_SLP_IE SENSE2_SLP_SEL SENSE2_FUN_SEL SENSE1_FUN_IE SENSE1_SLP_IE SENSE1_SLP_SEL SENSE1_FUN_SEL SENSE4_MUX_SEL SENSE3_MUX_SEL SENSE2_MUX_SEL SENSE1_MUX_SEL SENSE4_HOLD SENSE3_HOLD SENSE2_HOLD SENSE1_HOLD

SENSE4_FUN_IE :
bits : 4 - 4 (1 bit)

SENSE4_SLP_IE :
bits : 5 - 5 (1 bit)

SENSE4_SLP_SEL :
bits : 6 - 6 (1 bit)

SENSE4_FUN_SEL :
bits : 7 - 8 (2 bit)

SENSE3_FUN_IE :
bits : 9 - 9 (1 bit)

SENSE3_SLP_IE :
bits : 10 - 10 (1 bit)

SENSE3_SLP_SEL :
bits : 11 - 11 (1 bit)

SENSE3_FUN_SEL :
bits : 12 - 13 (2 bit)

SENSE2_FUN_IE :
bits : 14 - 14 (1 bit)

SENSE2_SLP_IE :
bits : 15 - 15 (1 bit)

SENSE2_SLP_SEL :
bits : 16 - 16 (1 bit)

SENSE2_FUN_SEL :
bits : 17 - 18 (2 bit)

SENSE1_FUN_IE :
bits : 19 - 19 (1 bit)

SENSE1_SLP_IE :
bits : 20 - 20 (1 bit)

SENSE1_SLP_SEL :
bits : 21 - 21 (1 bit)

SENSE1_FUN_SEL :
bits : 22 - 23 (2 bit)

SENSE4_MUX_SEL :
bits : 24 - 24 (1 bit)

SENSE3_MUX_SEL :
bits : 25 - 25 (1 bit)

SENSE2_MUX_SEL :
bits : 26 - 26 (1 bit)

SENSE1_MUX_SEL :
bits : 27 - 27 (1 bit)

SENSE4_HOLD :
bits : 28 - 28 (1 bit)

SENSE3_HOLD :
bits : 29 - 29 (1 bit)

SENSE2_HOLD :
bits : 30 - 30 (1 bit)

SENSE1_HOLD :
bits : 31 - 31 (1 bit)


OUT_W1TC

RTC_GPIO_OUT_W1TC
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUT_W1TC OUT_W1TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_DATA_W1TC

OUT_DATA_W1TC :
bits : 14 - 31 (18 bit)


ADC_PAD

RTC_IO_ADC_PAD
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_PAD ADC_PAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC2_FUN_IE ADC2_SLP_IE ADC2_SLP_SEL ADC2_FUN_SEL ADC1_FUN_IE ADC1_SLP_IE ADC1_SLP_SEL ADC1_FUN_SEL ADC2_MUX_SEL ADC1_MUX_SEL ADC2_HOLD ADC1_HOLD

ADC2_FUN_IE :
bits : 18 - 18 (1 bit)

ADC2_SLP_IE :
bits : 19 - 19 (1 bit)

ADC2_SLP_SEL :
bits : 20 - 20 (1 bit)

ADC2_FUN_SEL :
bits : 21 - 22 (2 bit)

ADC1_FUN_IE :
bits : 23 - 23 (1 bit)

ADC1_SLP_IE :
bits : 24 - 24 (1 bit)

ADC1_SLP_SEL :
bits : 25 - 25 (1 bit)

ADC1_FUN_SEL :
bits : 26 - 27 (2 bit)

ADC2_MUX_SEL :
bits : 28 - 28 (1 bit)

ADC1_MUX_SEL :
bits : 29 - 29 (1 bit)

ADC2_HOLD :
bits : 30 - 30 (1 bit)

ADC1_HOLD :
bits : 31 - 31 (1 bit)


PAD_DAC1

RTC_IO_PAD_DAC1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAD_DAC1 PAD_DAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDAC1_DAC_XPD_FORCE PDAC1_FUN_IE PDAC1_SLP_OE PDAC1_SLP_IE PDAC1_SLP_SEL PDAC1_FUN_SEL PDAC1_MUX_SEL PDAC1_XPD_DAC PDAC1_DAC PDAC1_RUE PDAC1_RDE PDAC1_HOLD PDAC1_DRV

PDAC1_DAC_XPD_FORCE :
bits : 10 - 10 (1 bit)

PDAC1_FUN_IE :
bits : 11 - 11 (1 bit)

PDAC1_SLP_OE :
bits : 12 - 12 (1 bit)

PDAC1_SLP_IE :
bits : 13 - 13 (1 bit)

PDAC1_SLP_SEL :
bits : 14 - 14 (1 bit)

PDAC1_FUN_SEL :
bits : 15 - 16 (2 bit)

PDAC1_MUX_SEL :
bits : 17 - 17 (1 bit)

PDAC1_XPD_DAC :
bits : 18 - 18 (1 bit)

PDAC1_DAC :
bits : 19 - 26 (8 bit)

PDAC1_RUE :
bits : 27 - 27 (1 bit)

PDAC1_RDE :
bits : 28 - 28 (1 bit)

PDAC1_HOLD :
bits : 29 - 29 (1 bit)

PDAC1_DRV :
bits : 30 - 31 (2 bit)


PAD_DAC2

RTC_IO_PAD_DAC2
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAD_DAC2 PAD_DAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDAC2_DAC_XPD_FORCE PDAC2_FUN_IE PDAC2_SLP_OE PDAC2_SLP_IE PDAC2_SLP_SEL PDAC2_FUN_SEL PDAC2_MUX_SEL PDAC2_XPD_DAC PDAC2_DAC PDAC2_RUE PDAC2_RDE PDAC2_HOLD PDAC2_DRV

PDAC2_DAC_XPD_FORCE :
bits : 10 - 10 (1 bit)

PDAC2_FUN_IE :
bits : 11 - 11 (1 bit)

PDAC2_SLP_OE :
bits : 12 - 12 (1 bit)

PDAC2_SLP_IE :
bits : 13 - 13 (1 bit)

PDAC2_SLP_SEL :
bits : 14 - 14 (1 bit)

PDAC2_FUN_SEL :
bits : 15 - 16 (2 bit)

PDAC2_MUX_SEL :
bits : 17 - 17 (1 bit)

PDAC2_XPD_DAC :
bits : 18 - 18 (1 bit)

PDAC2_DAC :
bits : 19 - 26 (8 bit)

PDAC2_RUE :
bits : 27 - 27 (1 bit)

PDAC2_RDE :
bits : 28 - 28 (1 bit)

PDAC2_HOLD :
bits : 29 - 29 (1 bit)

PDAC2_DRV :
bits : 30 - 31 (2 bit)


XTAL_32K_PAD

RTC_IO_XTAL_32K_PAD
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL_32K_PAD XTAL_32K_PAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBIAS_XTAL_32K DRES_XTAL_32K X32P_FUN_IE X32P_SLP_OE X32P_SLP_IE X32P_SLP_SEL X32P_FUN_SEL X32N_FUN_IE X32N_SLP_OE X32N_SLP_IE X32N_SLP_SEL X32N_FUN_SEL X32P_MUX_SEL X32N_MUX_SEL XPD_XTAL_32K DAC_XTAL_32K X32P_RUE X32P_RDE X32P_HOLD X32P_DRV X32N_RUE X32N_RDE X32N_HOLD X32N_DRV

DBIAS_XTAL_32K :
bits : 1 - 2 (2 bit)

DRES_XTAL_32K :
bits : 3 - 4 (2 bit)

X32P_FUN_IE :
bits : 5 - 5 (1 bit)

X32P_SLP_OE :
bits : 6 - 6 (1 bit)

X32P_SLP_IE :
bits : 7 - 7 (1 bit)

X32P_SLP_SEL :
bits : 8 - 8 (1 bit)

X32P_FUN_SEL :
bits : 9 - 10 (2 bit)

X32N_FUN_IE :
bits : 11 - 11 (1 bit)

X32N_SLP_OE :
bits : 12 - 12 (1 bit)

X32N_SLP_IE :
bits : 13 - 13 (1 bit)

X32N_SLP_SEL :
bits : 14 - 14 (1 bit)

X32N_FUN_SEL :
bits : 15 - 16 (2 bit)

X32P_MUX_SEL :
bits : 17 - 17 (1 bit)

X32N_MUX_SEL :
bits : 18 - 18 (1 bit)

XPD_XTAL_32K :
bits : 19 - 19 (1 bit)

DAC_XTAL_32K :
bits : 20 - 21 (2 bit)

X32P_RUE :
bits : 22 - 22 (1 bit)

X32P_RDE :
bits : 23 - 23 (1 bit)

X32P_HOLD :
bits : 24 - 24 (1 bit)

X32P_DRV :
bits : 25 - 26 (2 bit)

X32N_RUE :
bits : 27 - 27 (1 bit)

X32N_RDE :
bits : 28 - 28 (1 bit)

X32N_HOLD :
bits : 29 - 29 (1 bit)

X32N_DRV :
bits : 30 - 31 (2 bit)


TOUCH_CFG

RTC_IO_TOUCH_CFG
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_CFG TOUCH_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUCH_DCUR TOUCH_DRANGE TOUCH_DREFL TOUCH_DREFH TOUCH_XPD_BIAS

TOUCH_DCUR :
bits : 23 - 24 (2 bit)

TOUCH_DRANGE :
bits : 25 - 26 (2 bit)

TOUCH_DREFL :
bits : 27 - 28 (2 bit)

TOUCH_DREFH :
bits : 29 - 30 (2 bit)

TOUCH_XPD_BIAS :
bits : 31 - 31 (1 bit)


TOUCH_PAD0

RTC_IO_TOUCH_PAD0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD0 TOUCH_PAD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD1

RTC_IO_TOUCH_PAD1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD1 TOUCH_PAD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD2

RTC_IO_TOUCH_PAD2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD2 TOUCH_PAD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD3

RTC_IO_TOUCH_PAD3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD3 TOUCH_PAD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD4

RTC_IO_TOUCH_PAD4
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD4 TOUCH_PAD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD5

RTC_IO_TOUCH_PAD5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD5 TOUCH_PAD5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


PIN2

RTC_GPIO_PIN0
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN2 PIN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)


TOUCH_PAD6

RTC_IO_TOUCH_PAD6
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD6 TOUCH_PAD6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD7

RTC_IO_TOUCH_PAD7
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD7 TOUCH_PAD7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO FUN_IE SLP_OE SLP_IE SLP_SEL FUN_SEL MUX_SEL XPD TIE_OPT START DAC RUE RDE DRV HOLD

TO_GPIO :
bits : 12 - 12 (1 bit)

FUN_IE :
bits : 13 - 13 (1 bit)

SLP_OE :
bits : 14 - 14 (1 bit)

SLP_IE :
bits : 15 - 15 (1 bit)

SLP_SEL :
bits : 16 - 16 (1 bit)

FUN_SEL :
bits : 17 - 18 (2 bit)

MUX_SEL :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)

RUE :
bits : 27 - 27 (1 bit)

RDE :
bits : 28 - 28 (1 bit)

DRV :
bits : 29 - 30 (2 bit)

HOLD :
bits : 31 - 31 (1 bit)


TOUCH_PAD8

RTC_IO_TOUCH_PAD8
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD8 TOUCH_PAD8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO XPD TIE_OPT START DAC

TO_GPIO :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)


TOUCH_PAD9

RTC_IO_TOUCH_PAD9
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUCH_PAD9 TOUCH_PAD9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_GPIO XPD TIE_OPT START DAC

TO_GPIO :
bits : 19 - 19 (1 bit)

XPD :
bits : 20 - 20 (1 bit)

TIE_OPT :
bits : 21 - 21 (1 bit)

START :
bits : 22 - 22 (1 bit)

DAC :
bits : 23 - 25 (3 bit)


EXT_WAKEUP0

RTC_IO_EXT_WAKEUP0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXT_WAKEUP0 EXT_WAKEUP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXT_WAKEUP0_SEL

EXT_WAKEUP0_SEL :
bits : 27 - 31 (5 bit)


ENABLE

RTC_GPIO_ENABLE
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE :
bits : 14 - 31 (18 bit)


XTL_EXT_CTR

RTC_IO_XTL_EXT_CTR
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTL_EXT_CTR XTL_EXT_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL_EXT_CTR_SEL

XTL_EXT_CTR_SEL :
bits : 27 - 31 (5 bit)


SAR_I2C_IO

RTC_IO_SAR_I2C_IO
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR_I2C_IO SAR_I2C_IO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAR_DEBUG_BIT_SEL SAR_I2C_SCL_SEL SAR_I2C_SDA_SEL

SAR_DEBUG_BIT_SEL :
bits : 23 - 27 (5 bit)

SAR_I2C_SCL_SEL :
bits : 28 - 29 (2 bit)

SAR_I2C_SDA_SEL :
bits : 30 - 31 (2 bit)


DATE

RTC_IO_DATE
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO_DATE

IO_DATE :
bits : 0 - 27 (28 bit)


PIN3

RTC_GPIO_PIN0
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN3 PIN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_DRIVER INT_TYPE WAKEUP_ENABLE

PAD_DRIVER :
bits : 2 - 2 (1 bit)

INT_TYPE :
bits : 7 - 9 (3 bit)

WAKEUP_ENABLE :
bits : 10 - 10 (1 bit)



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