Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2DE0 byte (0x0)
mem_usage : registers
protection : not protected
DPORT_PRO_BOOT_REMAP_CTRL
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_BOOT_REMAP :
bits : 0 - 0 (1 bit)
DPORT_PRO_DPORT_APB_MASK1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRODPORT_APB_MASK1 :
bits : 0 - 31 (32 bit)
DPORT_APP_INTR_STATUS_2
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_INTR_STATUS_2 :
bits : 0 - 31 (32 bit)
DPORT_PRO_MAC_INTR_MAP
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_MAC_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_MAC_NMI_MAP
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_MAC_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_BB_INT_MAP
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_BB_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_BT_MAC_INT_MAP
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_BT_MAC_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_BT_BB_INT_MAP
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_BT_BB_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_BT_BB_NMI_MAP
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_BT_BB_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_RWBT_IRQ_MAP
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RWBT_IRQ_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_RWBLE_IRQ_MAP
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RWBLE_IRQ_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_RWBT_NMI_MAP
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RWBT_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_RWBLE_NMI_MAP
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RWBLE_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SLC0_INTR_MAP
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SLC0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SLC1_INTR_MAP
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SLC1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_UHCI0_INTR_MAP
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_UHCI0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_UHCI1_INTR_MAP
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_UHCI1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_T0_LEVEL_INT_MAP
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_T0_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_DPORT_APB_MASK0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPDPORT_APB_MASK0 :
bits : 0 - 31 (32 bit)
DPORT_PRO_TG_T1_LEVEL_INT_MAP
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_T1_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_WDT_LEVEL_INT_MAP
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_WDT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_LACT_LEVEL_INT_MAP
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_LACT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_T0_LEVEL_INT_MAP
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_T0_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_T1_LEVEL_INT_MAP
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_T1_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_WDT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_LACT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_GPIO_INTERRUPT_MAP
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_GPIO_INTERRUPT_PRO_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_GPIO_INTERRUPT_NMI_MAP
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_GPIO_INTERRUPT_PRO_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_INTR_FROM_CPU_0_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_INTR_FROM_CPU_1_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_INTR_FROM_CPU_2_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_INTR_FROM_CPU_3_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SPI_INTR_0_MAP
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI_INTR_0_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SPI_INTR_1_MAP
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI_INTR_1_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SPI_INTR_2_MAP
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI_INTR_2_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_DPORT_APB_MASK1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPDPORT_APB_MASK1 :
bits : 0 - 31 (32 bit)
DPORT_PRO_SPI_INTR_3_MAP
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI_INTR_3_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_I2S0_INT_MAP
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_I2S0_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_I2S1_INT_MAP
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_I2S1_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_UART_INTR_MAP
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_UART_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_UART1_INTR_MAP
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_UART1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_UART2_INTR_MAP
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_UART2_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SDIO_HOST_INTERRUPT_MAP
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SDIO_HOST_INTERRUPT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_EMAC_INT_MAP
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_EMAC_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_PWM0_INTR_MAP
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_PWM0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_PWM1_INTR_MAP
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_PWM1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_PWM2_INTR_MAP
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_PWM2_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_PWM3_INTR_MAP
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_PWM3_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_LEDC_INT_MAP
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_LEDC_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_EFUSE_INT_MAP
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_EFUSE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_CAN_INT_MAP
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CAN_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_RTC_CORE_INTR_MAP
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RTC_CORE_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PERI_CLK_EN
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERI_CLK_EN :
bits : 0 - 31 (32 bit)
AES_ACCELERATOR :
bits : 0 - 0 (1 bit)
SHA_ACCELERATOR :
bits : 1 - 1 (1 bit)
RSA_ACCELERATOR :
bits : 2 - 2 (1 bit)
SECURE_BOOT :
bits : 3 - 3 (1 bit)
DIGITAL_SIGNATURE :
bits : 4 - 4 (1 bit)
DPORT_PRO_RMT_INTR_MAP
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RMT_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_PCNT_INTR_MAP
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_PCNT_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_I2C_EXT0_INTR_MAP
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_I2C_EXT0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_I2C_EXT1_INTR_MAP
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_I2C_EXT1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_RSA_INTR_MAP
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_RSA_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SPI1_DMA_INT_MAP
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI1_DMA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SPI2_DMA_INT_MAP
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI2_DMA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_SPI3_DMA_INT_MAP
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_SPI3_DMA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_WDG_INT_MAP
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_WDG_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TIMER_INT1_MAP
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TIMER_INT1_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TIMER_INT2_MAP
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TIMER_INT2_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_T0_EDGE_INT_MAP
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_T0_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_T1_EDGE_INT_MAP
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_T1_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_WDT_EDGE_INT_MAP
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_WDT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG_LACT_EDGE_INT_MAP
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG_LACT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_T0_EDGE_INT_MAP
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_T0_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PERI_RST_EN
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERI_RST_EN :
bits : 0 - 31 (32 bit)
AES_ACCELERATOR :
bits : 0 - 0 (1 bit)
SHA_ACCELERATOR :
bits : 1 - 1 (1 bit)
RSA_ACCELERATOR :
bits : 2 - 2 (1 bit)
SECURE_BOOT :
bits : 3 - 3 (1 bit)
DIGITAL_SIGNATURE :
bits : 4 - 4 (1 bit)
DPORT_PRO_TG1_T1_EDGE_INT_MAP
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_T1_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_WDT_EDGE_INT_MAP
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_WDT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_TG1_LACT_EDGE_INT_MAP
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TG1_LACT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_MMU_IA_INT_MAP
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_MMU_IA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_MPU_IA_INT_MAP
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_MPU_IA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_PRO_CACHE_IA_INT_MAP
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_IA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_MAC_INTR_MAP
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_MAC_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_MAC_NMI_MAP
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_MAC_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_BB_INT_MAP
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_BB_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_BT_MAC_INT_MAP
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_BT_MAC_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_BT_BB_INT_MAP
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_BT_BB_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_BT_BB_NMI_MAP
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_BT_BB_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RWBT_IRQ_MAP
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RWBT_IRQ_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RWBLE_IRQ_MAP
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RWBLE_IRQ_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RWBT_NMI_MAP
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RWBT_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RWBLE_NMI_MAP
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RWBLE_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_WIFI_BB_CFG
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIFI_BB_CFG :
bits : 0 - 31 (32 bit)
DPORT_APP_SLC0_INTR_MAP
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SLC0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SLC1_INTR_MAP
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SLC1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_UHCI0_INTR_MAP
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_UHCI0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_UHCI1_INTR_MAP
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_UHCI1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_T0_LEVEL_INT_MAP
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_T0_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_T1_LEVEL_INT_MAP
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_T1_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_WDT_LEVEL_INT_MAP
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_WDT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_LACT_LEVEL_INT_MAP
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_LACT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_T0_LEVEL_INT_MAP
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_T0_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_T1_LEVEL_INT_MAP
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_T1_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_WDT_LEVEL_INT_MAP
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_WDT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_LACT_LEVEL_INT_MAP
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_LACT_LEVEL_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_GPIO_INTERRUPT_MAP
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_GPIO_INTERRUPT_APP_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_GPIO_INTERRUPT_NMI_MAP
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_GPIO_INTERRUPT_APP_NMI_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_CPU_INTR_FROM_CPU_0_MAP
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_INTR_FROM_CPU_0_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_CPU_INTR_FROM_CPU_1_MAP
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_INTR_FROM_CPU_1_MAP :
bits : 0 - 4 (5 bit)
DPORT_WIFI_BB_CFG_2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIFI_BB_CFG_2 :
bits : 0 - 31 (32 bit)
DPORT_APP_CPU_INTR_FROM_CPU_2_MAP
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_INTR_FROM_CPU_2_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_CPU_INTR_FROM_CPU_3_MAP
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_INTR_FROM_CPU_3_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI_INTR_0_MAP
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI_INTR_0_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI_INTR_1_MAP
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI_INTR_1_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI_INTR_2_MAP
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI_INTR_2_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI_INTR_3_MAP
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI_INTR_3_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_I2S0_INT_MAP
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_I2S0_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_I2S1_INT_MAP
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_I2S1_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_UART_INTR_MAP
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_UART_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_UART1_INTR_MAP
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_UART1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_UART2_INTR_MAP
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_UART2_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SDIO_HOST_INTERRUPT_MAP
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SDIO_HOST_INTERRUPT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_EMAC_INT_MAP
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_EMAC_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_PWM0_INTR_MAP
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_PWM0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_PWM1_INTR_MAP
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_PWM1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_PWM2_INTR_MAP
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_PWM2_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APPCPU_CTRL_A
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPCPU_RESETTING :
bits : 0 - 0 (1 bit)
DPORT_APP_PWM3_INTR_MAP
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_PWM3_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_LEDC_INT_MAP
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_LEDC_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_EFUSE_INT_MAP
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_EFUSE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_CAN_INT_MAP
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CAN_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RTC_CORE_INTR_MAP
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RTC_CORE_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RMT_INTR_MAP
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RMT_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_PCNT_INTR_MAP
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_PCNT_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_I2C_EXT0_INTR_MAP
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_I2C_EXT0_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_I2C_EXT1_INTR_MAP
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_I2C_EXT1_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_RSA_INTR_MAP
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_RSA_INTR_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI1_DMA_INT_MAP
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI1_DMA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI2_DMA_INT_MAP
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI2_DMA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_SPI3_DMA_INT_MAP
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_SPI3_DMA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_WDG_INT_MAP
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_WDG_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TIMER_INT1_MAP
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TIMER_INT1_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TIMER_INT2_MAP
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TIMER_INT2_MAP :
bits : 0 - 4 (5 bit)
DPORT_APPCPU_CTRL_B
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPCPU_CLKGATE_EN :
bits : 0 - 0 (1 bit)
DPORT_APP_TG_T0_EDGE_INT_MAP
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_T0_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_T1_EDGE_INT_MAP
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_T1_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_WDT_EDGE_INT_MAP
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_WDT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG_LACT_EDGE_INT_MAP
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG_LACT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_T0_EDGE_INT_MAP
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_T0_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_T1_EDGE_INT_MAP
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_T1_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_WDT_EDGE_INT_MAP
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_WDT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_TG1_LACT_EDGE_INT_MAP
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TG1_LACT_EDGE_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_MMU_IA_INT_MAP
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_MMU_IA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_MPU_IA_INT_MAP
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_MPU_IA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_APP_CACHE_IA_INT_MAP
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_IA_INT_MAP :
bits : 0 - 4 (5 bit)
DPORT_AHBLITE_MPU_TABLE_UART
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SPI1
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SPI0
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI0_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_GPIO
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_FE2
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FE2_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_APPCPU_CTRL_C
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPCPU_RUNSTALL :
bits : 0 - 0 (1 bit)
DPORT_AHBLITE_MPU_TABLE_FE
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FE_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_TIMER
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_RTC
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_IO_MUX
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOMUX_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_WDG
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDG_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_HINF
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HINF_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_UHCI1
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UHCI1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_MISC
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_I2C
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_I2S0
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S0_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_UART1
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_BT
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BT_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_BT_BUFFER
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTBUFFER_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_I2C_EXT0
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CEXT0_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_UHCI0
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UHCI0_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SLCHOST
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLCHOST_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_APPCPU_CTRL_D
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPCPU_BOOT_ADDR :
bits : 0 - 31 (32 bit)
DPORT_AHBLITE_MPU_TABLE_RMT
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMT_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_PCNT
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCNT_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SLC
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_LEDC
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEDC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_EFUSE
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFUSE_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI_ENCRYPY_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_BB
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BB_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_PWM0
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_TIMERGROUP
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMERGROUP_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMERGROUP1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SPI2
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI2_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SPI3
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI3_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_APB_CTRL
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBCTRL_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_I2C_EXT1
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CEXT1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_SDIO_HOST
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIOHOST_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_EMAC
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_CPU_PER_CONF
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUPERIOD_SEL :
bits : 0 - 1 (2 bit)
Enumeration: CPUPERIOD_SEL ( read-write )
0 : SEL_80
Select 80 MHz clock
1 : SEL_160
Select 160 MHz clock
2 : SEL_240
Select 240 MHz clock
End of enumeration elements list.
LOWSPEED_CLK_SEL :
bits : 2 - 2 (1 bit)
FAST_CLK_RTC_SEL :
bits : 3 - 3 (1 bit)
DPORT_AHBLITE_MPU_TABLE_CAN
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAN_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_PWM1
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_I2S1
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S1_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_UART2
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART2_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_PWM2
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_PWM3
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_RWBT
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWBT_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_BTMAC
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTMAC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_WIFIMAC
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIFIMAC_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_AHBLITE_MPU_TABLE_PWR
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_ACCESS_GRANT_CONFIG :
bits : 0 - 5 (6 bit)
DPORT_MEM_ACCESS_DBUG0
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_ROM_MPU_AD :
bits : 0 - 0 (1 bit)
PRO_ROM_IA :
bits : 1 - 1 (1 bit)
APP_ROM_MPU_AD :
bits : 2 - 2 (1 bit)
APP_ROM_IA :
bits : 3 - 3 (1 bit)
SHARE_ROM_MPU_AD :
bits : 4 - 5 (2 bit)
SHARE_ROM_IA :
bits : 6 - 9 (4 bit)
INTERNAL_SRAM_MMU_AD :
bits : 10 - 13 (4 bit)
INTERNAL_SRAM_IA :
bits : 14 - 25 (12 bit)
INTERNAL_SRAM_MMU_MULTI_HIT :
bits : 26 - 29 (4 bit)
DPORT_MEM_ACCESS_DBUG1
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERNAL_SRAM_MMU_MISS :
bits : 0 - 3 (4 bit)
ARB_IA :
bits : 4 - 5 (2 bit)
PIDGEN_IA :
bits : 6 - 7 (2 bit)
AHB_ACCESS_DENY :
bits : 8 - 8 (1 bit)
AHBLITE_ACCESS_DENY :
bits : 9 - 9 (1 bit)
AHBLITE_IA :
bits : 10 - 10 (1 bit)
DPORT_PRO_DCACHE_DBUG0
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_MMU_IA :
bits : 0 - 0 (1 bit)
PRO_CACHE_IA :
bits : 1 - 6 (6 bit)
PRO_CACHE_STATE :
bits : 7 - 18 (12 bit)
PRO_WR_BAK_TO_READ :
bits : 19 - 19 (1 bit)
PRO_TX_END :
bits : 20 - 20 (1 bit)
PRO_SLAVE_WR :
bits : 21 - 21 (1 bit)
PRO_SLAVE_WDATA_V :
bits : 22 - 22 (1 bit)
PRO_RX_END :
bits : 23 - 23 (1 bit)
DPORT_PRO_DCACHE_DBUG1
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CTAG_RAM_RDATA :
bits : 0 - 31 (32 bit)
DPORT_PRO_DCACHE_DBUG2
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_VADDR :
bits : 0 - 26 (27 bit)
DPORT_PRO_DCACHE_DBUG3
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_DISABLED_CACHE_IA :
bits : 9 - 14 (6 bit)
PRO_CACHE_IRAM0_PID_ERROR :
bits : 15 - 15 (1 bit)
DPORT_APP_BOOT_REMAP_CTRL
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_BOOT_REMAP :
bits : 0 - 0 (1 bit)
DPORT_PRO_CACHE_CTRL
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_MODE :
bits : 2 - 2 (1 bit)
PRO_CACHE_ENABLE :
bits : 3 - 3 (1 bit)
PRO_CACHE_FLUSH_ENA :
bits : 4 - 4 (1 bit)
PRO_CACHE_FLUSH_DONE :
bits : 5 - 5 (1 bit)
PRO_CACHE_LOCK_0_EN :
bits : 6 - 6 (1 bit)
PRO_CACHE_LOCK_1_EN :
bits : 7 - 7 (1 bit)
PRO_CACHE_LOCK_2_EN :
bits : 8 - 8 (1 bit)
PRO_CACHE_LOCK_3_EN :
bits : 9 - 9 (1 bit)
PRO_SINGLE_IRAM_ENA :
bits : 10 - 10 (1 bit)
PRO_DRAM_SPLIT :
bits : 11 - 11 (1 bit)
PRO_AHB_SPI_REQ :
bits : 12 - 12 (1 bit)
PRO_SLAVE_REQ :
bits : 13 - 13 (1 bit)
AHB_SPI_REQ :
bits : 14 - 14 (1 bit)
SLAVE_REQ :
bits : 15 - 15 (1 bit)
PRO_DRAM_HL :
bits : 16 - 16 (1 bit)
DPORT_PRO_DCACHE_DBUG4
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_DRAM1ADDR0_IA :
bits : 0 - 19 (20 bit)
DPORT_PRO_DCACHE_DBUG5
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_DROM0ADDR0_IA :
bits : 0 - 19 (20 bit)
DPORT_PRO_DCACHE_DBUG6
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_IRAM0ADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_PRO_DCACHE_DBUG7
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_IRAM1ADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_PRO_DCACHE_DBUG8
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_IROM0ADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_PRO_DCACHE_DBUG9
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_OPSDRAMADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_APP_DCACHE_DBUG0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_MMU_IA :
bits : 0 - 0 (1 bit)
APP_CACHE_IA :
bits : 1 - 6 (6 bit)
APP_CACHE_STATE :
bits : 7 - 18 (12 bit)
APP_WR_BAK_TO_READ :
bits : 19 - 19 (1 bit)
APP_TX_END :
bits : 20 - 20 (1 bit)
APP_SLAVE_WR :
bits : 21 - 21 (1 bit)
APP_SLAVE_WDATA_V :
bits : 22 - 22 (1 bit)
APP_RX_END :
bits : 23 - 23 (1 bit)
DPORT_APP_DCACHE_DBUG1
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CTAG_RAM_RDATA :
bits : 0 - 31 (32 bit)
DPORT_APP_DCACHE_DBUG2
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_VADDR :
bits : 0 - 26 (27 bit)
DPORT_APP_DCACHE_DBUG3
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_DISABLED_CACHE_IA :
bits : 9 - 14 (6 bit)
APP_CACHE_IRAM0_PID_ERROR :
bits : 15 - 15 (1 bit)
DPORT_APP_DCACHE_DBUG4
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_DRAM1ADDR0_IA :
bits : 0 - 19 (20 bit)
DPORT_APP_DCACHE_DBUG5
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_DROM0ADDR0_IA :
bits : 0 - 19 (20 bit)
DPORT_APP_DCACHE_DBUG6
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_IRAM0ADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_APP_DCACHE_DBUG7
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_IRAM1ADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_APP_DCACHE_DBUG8
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_IROM0ADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_APP_DCACHE_DBUG9
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_OPSDRAMADDR_IA :
bits : 0 - 19 (20 bit)
DPORT_PRO_CACHE_CTRL1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_MASK_IRAM0 :
bits : 0 - 0 (1 bit)
PRO_CACHE_MASK_IRAM1 :
bits : 1 - 1 (1 bit)
PRO_CACHE_MASK_IROM0 :
bits : 2 - 2 (1 bit)
PRO_CACHE_MASK_DRAM1 :
bits : 3 - 3 (1 bit)
PRO_CACHE_MASK_DROM0 :
bits : 4 - 4 (1 bit)
PRO_CACHE_MASK_OPSDRAM :
bits : 5 - 5 (1 bit)
PRO_CMMU_SRAM_PAGE_MODE :
bits : 6 - 8 (3 bit)
PRO_CMMU_FLASH_PAGE_MODE :
bits : 9 - 10 (2 bit)
PRO_CMMU_FORCE_ON :
bits : 11 - 11 (1 bit)
PRO_CMMU_PD :
bits : 12 - 12 (1 bit)
PRO_CACHE_MMU_IA_CLR :
bits : 13 - 13 (1 bit)
DPORT_PRO_CPU_RECORD_CTRL
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_RECORD_ENABLE :
bits : 0 - 0 (1 bit)
PRO_CPU_RECORD_DISABLE :
bits : 4 - 4 (1 bit)
PRO_CPU_PDEBUG_ENABLE :
bits : 8 - 8 (1 bit)
DPORT_PRO_CPU_RECORD_STATUS
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CPU_RECORDING :
bits : 0 - 0 (1 bit)
DPORT_PRO_CPU_RECORD_PID
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PID :
bits : 0 - 2 (3 bit)
DPORT_PRO_CPU_RECORD_PDEBUGINST
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGINST :
bits : 0 - 31 (32 bit)
DPORT_PRO_CPU_RECORD_PDEBUGSTATUS
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGSTATUS :
bits : 0 - 7 (8 bit)
DPORT_PRO_CPU_RECORD_PDEBUGDATA
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGDATA :
bits : 0 - 31 (32 bit)
DPORT_PRO_CPU_RECORD_PDEBUGPC
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGPC :
bits : 0 - 31 (32 bit)
DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGLS0STAT :
bits : 0 - 31 (32 bit)
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGLS0ADDR :
bits : 0 - 31 (32 bit)
DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_PRO_PDEBUGLS0DATA :
bits : 0 - 31 (32 bit)
DPORT_APP_CPU_RECORD_CTRL
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_RECORD_ENABLE :
bits : 0 - 0 (1 bit)
APP_CPU_RECORD_DISABLE :
bits : 4 - 4 (1 bit)
APP_CPU_PDEBUG_ENABLE :
bits : 8 - 8 (1 bit)
DPORT_APP_CPU_RECORD_STATUS
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CPU_RECORDING :
bits : 0 - 0 (1 bit)
DPORT_APP_CPU_RECORD_PID
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PID :
bits : 0 - 2 (3 bit)
DPORT_APP_CPU_RECORD_PDEBUGINST
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGINST :
bits : 0 - 31 (32 bit)
DPORT_APP_CPU_RECORD_PDEBUGSTATUS
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGSTATUS :
bits : 0 - 7 (8 bit)
DPORT_APP_CPU_RECORD_PDEBUGDATA
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGDATA :
bits : 0 - 31 (32 bit)
DPORT_PRO_CACHE_LOCK_0_ADDR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_LOCK_0_ADDR_PRE :
bits : 0 - 13 (14 bit)
PRO_CACHE_LOCK_0_ADDR_MIN :
bits : 14 - 17 (4 bit)
PRO_CACHE_LOCK_0_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_APP_CPU_RECORD_PDEBUGPC
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGPC :
bits : 0 - 31 (32 bit)
DPORT_APP_CPU_RECORD_PDEBUGLS0STAT
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGLS0STAT :
bits : 0 - 31 (32 bit)
DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGLS0ADDR :
bits : 0 - 31 (32 bit)
DPORT_APP_CPU_RECORD_PDEBUGLS0DATA
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECORD_APP_PDEBUGLS0DATA :
bits : 0 - 31 (32 bit)
DPORT_RSA_PD_CTRL
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSA_PD :
bits : 0 - 0 (1 bit)
DPORT_ROM_MPU_TABLE0
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROM_MPU_TABLE0 :
bits : 0 - 1 (2 bit)
DPORT_ROM_MPU_TABLE1
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROM_MPU_TABLE1 :
bits : 0 - 1 (2 bit)
DPORT_ROM_MPU_TABLE2
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROM_MPU_TABLE2 :
bits : 0 - 1 (2 bit)
DPORT_ROM_MPU_TABLE3
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROM_MPU_TABLE3 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE0
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE0 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE1
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE1 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE2
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE2 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE3
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE3 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE4
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE4 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE5
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE5 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE6
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE6 :
bits : 0 - 1 (2 bit)
DPORT_PRO_CACHE_LOCK_1_ADDR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_LOCK_1_ADDR_PRE :
bits : 0 - 13 (14 bit)
PRO_CACHE_LOCK_1_ADDR_MIN :
bits : 14 - 17 (4 bit)
PRO_CACHE_LOCK_1_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_SHROM_MPU_TABLE7
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE7 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE8
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE8 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE9
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE9 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE10
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE10 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE11
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE11 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE12
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE12 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE13
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE13 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE14
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE14 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE15
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE15 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE16
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE16 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE17
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE17 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE18
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE18 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE19
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE19 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE20
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE20 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE21
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE21 :
bits : 0 - 1 (2 bit)
DPORT_SHROM_MPU_TABLE22
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE22 :
bits : 0 - 1 (2 bit)
DPORT_PRO_CACHE_LOCK_2_ADDR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_LOCK_2_ADDR_PRE :
bits : 0 - 13 (14 bit)
PRO_CACHE_LOCK_2_ADDR_MIN :
bits : 14 - 17 (4 bit)
PRO_CACHE_LOCK_2_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_SHROM_MPU_TABLE23
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHROM_MPU_TABLE23 :
bits : 0 - 1 (2 bit)
DPORT_IMMU_TABLE0
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE0 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE1
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE1 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE2
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE2 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE3
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE3 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE4
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE4 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE5
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE5 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE6
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE6 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE7
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE7 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE8
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE8 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE9
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE9 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE10
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE10 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE11
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE11 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE12
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE12 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE13
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE13 :
bits : 0 - 6 (7 bit)
DPORT_IMMU_TABLE14
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE14 :
bits : 0 - 6 (7 bit)
DPORT_PRO_CACHE_LOCK_3_ADDR
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_LOCK_3_ADDR_PRE :
bits : 0 - 13 (14 bit)
PRO_CACHE_LOCK_3_ADDR_MIN :
bits : 14 - 17 (4 bit)
PRO_CACHE_LOCK_3_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_IMMU_TABLE15
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMMU_TABLE15 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE0
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE0 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE1
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE1 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE2
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE2 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE3
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE3 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE4
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE4 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE5
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE5 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE6
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE6 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE7
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE7 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE8
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE8 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE9
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE9 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE10
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE10 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE11
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE11 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE12
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE12 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE13
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE13 :
bits : 0 - 6 (7 bit)
DPORT_DMMU_TABLE14
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE14 :
bits : 0 - 6 (7 bit)
DPORT_APP_CACHE_CTRL
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_MODE :
bits : 2 - 2 (1 bit)
APP_CACHE_ENABLE :
bits : 3 - 3 (1 bit)
APP_CACHE_FLUSH_ENA :
bits : 4 - 4 (1 bit)
APP_CACHE_FLUSH_DONE :
bits : 5 - 5 (1 bit)
APP_CACHE_LOCK_0_EN :
bits : 6 - 6 (1 bit)
APP_CACHE_LOCK_1_EN :
bits : 7 - 7 (1 bit)
APP_CACHE_LOCK_2_EN :
bits : 8 - 8 (1 bit)
APP_CACHE_LOCK_3_EN :
bits : 9 - 9 (1 bit)
APP_SINGLE_IRAM_ENA :
bits : 10 - 10 (1 bit)
APP_DRAM_SPLIT :
bits : 11 - 11 (1 bit)
APP_AHB_SPI_REQ :
bits : 12 - 12 (1 bit)
APP_SLAVE_REQ :
bits : 13 - 13 (1 bit)
APP_DRAM_HL :
bits : 14 - 14 (1 bit)
DPORT_DMMU_TABLE15
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMMU_TABLE15 :
bits : 0 - 6 (7 bit)
DPORT_PRO_INTRUSION_CTRL
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_INTRUSION_RECORD_RESET_N :
bits : 0 - 0 (1 bit)
DPORT_PRO_INTRUSION_STATUS
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_INTRUSION_RECORD :
bits : 0 - 3 (4 bit)
DPORT_APP_INTRUSION_CTRL
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_INTRUSION_RECORD_RESET_N :
bits : 0 - 0 (1 bit)
DPORT_APP_INTRUSION_STATUS
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_INTRUSION_RECORD :
bits : 0 - 3 (4 bit)
DPORT_FRONT_END_MEM_PD
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_MEM_FORCE_PU :
bits : 0 - 0 (1 bit)
AGC_MEM_FORCE_PD :
bits : 1 - 1 (1 bit)
PBUS_MEM_FORCE_PU :
bits : 2 - 2 (1 bit)
PBUS_MEM_FORCE_PD :
bits : 3 - 3 (1 bit)
DPORT_MMU_IA_INT_EN
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMU_IA_INT_EN :
bits : 0 - 23 (24 bit)
DPORT_MPU_IA_INT_EN
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU_IA_INT_EN :
bits : 0 - 16 (17 bit)
DPORT_CACHE_IA_INT_EN
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_IA_INT_EN :
bits : 0 - 27 (28 bit)
CACHE_IA_INT_APP_DROM0 :
bits : 0 - 0 (1 bit)
CACHE_IA_INT_APP_IRAM0 :
bits : 1 - 1 (1 bit)
CACHE_IA_INT_APP_IRAM1 :
bits : 2 - 2 (1 bit)
CACHE_IA_INT_APP_IROM0 :
bits : 3 - 3 (1 bit)
CACHE_IA_INT_APP_OPPOSITE :
bits : 5 - 5 (1 bit)
CACHE_IA_INT_PRO_DROM0 :
bits : 14 - 14 (1 bit)
CACHE_IA_INT_PRO_IRAM0 :
bits : 15 - 15 (1 bit)
CACHE_IA_INT_PRO_IRAM1 :
bits : 16 - 16 (1 bit)
CACHE_IA_INT_PRO_IROM0 :
bits : 17 - 17 (1 bit)
CACHE_IA_INT_PRO_DRAM1 :
bits : 18 - 18 (1 bit)
CACHE_IA_INT_PRO_OPPOSITE :
bits : 19 - 19 (1 bit)
DPORT_SECURE_BOOT_CTRL
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_BOOTLOADER_SEL :
bits : 0 - 0 (1 bit)
DPORT_SPI_DMA_CHAN_SEL
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1_DMA_CHAN_SEL :
bits : 0 - 1 (2 bit)
SPI2_DMA_CHAN_SEL :
bits : 2 - 3 (2 bit)
SPI3_DMA_CHAN_SEL :
bits : 4 - 5 (2 bit)
DPORT_PRO_VECBASE_CTRL
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_OUT_VECBASE_SEL :
bits : 0 - 1 (2 bit)
DPORT_PRO_VECBASE_SET
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_OUT_VECBASE_REG :
bits : 0 - 21 (22 bit)
DPORT_APP_VECBASE_CTRL
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_OUT_VECBASE_SEL :
bits : 0 - 1 (2 bit)
DPORT_APP_VECBASE_SET
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_OUT_VECBASE_REG :
bits : 0 - 21 (22 bit)
DPORT_APP_CACHE_CTRL1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_MASK_IRAM0 :
bits : 0 - 0 (1 bit)
APP_CACHE_MASK_IRAM1 :
bits : 1 - 1 (1 bit)
APP_CACHE_MASK_IROM0 :
bits : 2 - 2 (1 bit)
APP_CACHE_MASK_DRAM1 :
bits : 3 - 3 (1 bit)
APP_CACHE_MASK_DROM0 :
bits : 4 - 4 (1 bit)
APP_CACHE_MASK_OPSDRAM :
bits : 5 - 5 (1 bit)
APP_CMMU_SRAM_PAGE_MODE :
bits : 6 - 8 (3 bit)
APP_CMMU_FLASH_PAGE_MODE :
bits : 9 - 10 (2 bit)
APP_CMMU_FORCE_ON :
bits : 11 - 11 (1 bit)
APP_CMMU_PD :
bits : 12 - 12 (1 bit)
APP_CACHE_MMU_IA_CLR :
bits : 13 - 13 (1 bit)
DPORT_APP_CACHE_LOCK_0_ADDR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_LOCK_0_ADDR_PRE :
bits : 0 - 13 (14 bit)
APP_CACHE_LOCK_0_ADDR_MIN :
bits : 14 - 17 (4 bit)
APP_CACHE_LOCK_0_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_APP_CACHE_LOCK_1_ADDR
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_LOCK_1_ADDR_PRE :
bits : 0 - 13 (14 bit)
APP_CACHE_LOCK_1_ADDR_MIN :
bits : 14 - 17 (4 bit)
APP_CACHE_LOCK_1_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_APP_CACHE_LOCK_2_ADDR
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_LOCK_2_ADDR_PRE :
bits : 0 - 13 (14 bit)
APP_CACHE_LOCK_2_ADDR_MIN :
bits : 14 - 17 (4 bit)
APP_CACHE_LOCK_2_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_APP_CACHE_LOCK_3_ADDR
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_CACHE_LOCK_3_ADDR_PRE :
bits : 0 - 13 (14 bit)
APP_CACHE_LOCK_3_ADDR_MIN :
bits : 14 - 17 (4 bit)
APP_CACHE_LOCK_3_ADDR_MAX :
bits : 18 - 21 (4 bit)
DPORT_TRACEMEM_MUX_MODE
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACEMEM_MUX_MODE :
bits : 0 - 1 (2 bit)
DPORT_PRO_TRACEMEM_ENA
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_TRACEMEM_ENA :
bits : 0 - 0 (1 bit)
DPORT_APP_TRACEMEM_ENA
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_TRACEMEM_ENA :
bits : 0 - 0 (1 bit)
DPORT_CACHE_MUX_MODE
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_MUX_MODE :
bits : 0 - 1 (2 bit)
DPORT_ACCESS_CHECK
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCESS_CHECK_PRO :
bits : 0 - 0 (1 bit)
ACCESS_CHECK_APP :
bits : 8 - 8 (1 bit)
DPORT_IMMU_PAGE_MODE
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERNAL_SRAM_IMMU_ENA :
bits : 0 - 0 (1 bit)
IMMU_PAGE_MODE :
bits : 1 - 2 (2 bit)
DPORT_DMMU_PAGE_MODE
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERNAL_SRAM_DMMU_ENA :
bits : 0 - 0 (1 bit)
DMMU_PAGE_MODE :
bits : 1 - 2 (2 bit)
DPORT_ROM_MPU_ENA
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHARE_ROM_MPU_ENA :
bits : 0 - 0 (1 bit)
PRO_ROM_MPU_ENA :
bits : 1 - 1 (1 bit)
APP_ROM_MPU_ENA :
bits : 2 - 2 (1 bit)
DPORT_MEM_PD_MASK
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSLP_MEM_PD_MASK :
bits : 0 - 0 (1 bit)
DPORT_ROM_PD_CTRL
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_ROM_PD :
bits : 0 - 0 (1 bit)
APP_ROM_PD :
bits : 1 - 1 (1 bit)
SHARE_ROM_PD :
bits : 2 - 7 (6 bit)
DPORT_ROM_FO_CTRL
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_ROM_FO :
bits : 0 - 0 (1 bit)
APP_ROM_FO :
bits : 1 - 1 (1 bit)
SHARE_ROM_FO :
bits : 2 - 7 (6 bit)
DPORT_SRAM_PD_CTRL_0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_PD_0 :
bits : 0 - 31 (32 bit)
DPORT_SRAM_PD_CTRL_1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_PD_1 :
bits : 0 - 0 (1 bit)
DPORT_SRAM_FO_CTRL_0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_FO_0 :
bits : 0 - 31 (32 bit)
DPORT_SRAM_FO_CTRL_1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_FO_1 :
bits : 0 - 0 (1 bit)
DPORT_IRAM_DRAM_AHB_SEL
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK_PRO_IRAM :
bits : 0 - 0 (1 bit)
MASK_APP_IRAM :
bits : 1 - 1 (1 bit)
MASK_PRO_DRAM :
bits : 2 - 2 (1 bit)
MASK_APP_DRAM :
bits : 3 - 3 (1 bit)
MASK_AHB :
bits : 4 - 4 (1 bit)
MAC_DUMP_MODE :
bits : 5 - 6 (2 bit)
DPORT_TAG_FO_CTRL
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_CACHE_TAG_FORCE_ON :
bits : 0 - 0 (1 bit)
PRO_CACHE_TAG_PD :
bits : 1 - 1 (1 bit)
APP_CACHE_TAG_FORCE_ON :
bits : 8 - 8 (1 bit)
APP_CACHE_TAG_PD :
bits : 9 - 9 (1 bit)
DPORT_AHB_LITE_MASK
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHB_LITE_MASK_PRO :
bits : 0 - 0 (1 bit)
AHB_LITE_MASK_APP :
bits : 4 - 4 (1 bit)
AHB_LITE_MASK_SDIO :
bits : 8 - 8 (1 bit)
AHB_LITE_MASK_PRODPORT :
bits : 9 - 9 (1 bit)
AHB_LITE_MASK_APPDPORT :
bits : 10 - 10 (1 bit)
AHB_LITE_SDHOST_PID_REG :
bits : 11 - 13 (3 bit)
DPORT_AHB_MPU_TABLE_0
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHB_ACCESS_GRANT_0 :
bits : 0 - 31 (32 bit)
DPORT_AHB_MPU_TABLE_1
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHB_ACCESS_GRANT_1 :
bits : 0 - 8 (9 bit)
DPORT_HOST_INF_SEL
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERI_IO_SWAP :
bits : 0 - 7 (8 bit)
LINK_DEVICE_SEL :
bits : 8 - 15 (8 bit)
DPORT_PRO_DPORT_APB_MASK0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRODPORT_APB_MASK0 :
bits : 0 - 31 (32 bit)
DPORT_PERIP_CLK_EN
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIP_CLK_EN :
bits : 0 - 31 (32 bit)
TIMERS :
bits : 0 - 0 (1 bit)
SPI0 :
bits : 1 - 1 (1 bit)
UART0 :
bits : 2 - 2 (1 bit)
WDG :
bits : 3 - 3 (1 bit)
I2S0 :
bits : 4 - 4 (1 bit)
UART1 :
bits : 5 - 5 (1 bit)
SPI2 :
bits : 6 - 6 (1 bit)
I2C0 :
bits : 7 - 7 (1 bit)
UHCI0 :
bits : 8 - 8 (1 bit)
REMOTE_CONTROLLER :
bits : 9 - 9 (1 bit)
PULSE_CNT :
bits : 10 - 10 (1 bit)
LED_PWM :
bits : 11 - 11 (1 bit)
UHCI1 :
bits : 12 - 12 (1 bit)
TIMER_GROUP0 :
bits : 13 - 13 (1 bit)
EFUSE :
bits : 14 - 14 (1 bit)
TIMER_GROUP1 :
bits : 15 - 15 (1 bit)
SPI3 :
bits : 16 - 16 (1 bit)
PWM0 :
bits : 17 - 17 (1 bit)
I2C1 :
bits : 18 - 18 (1 bit)
CAN :
bits : 19 - 19 (1 bit)
PWM1 :
bits : 20 - 20 (1 bit)
I2S1 :
bits : 21 - 21 (1 bit)
SPI_DMA :
bits : 22 - 22 (1 bit)
UART2 :
bits : 23 - 23 (1 bit)
UART_MEM :
bits : 24 - 24 (1 bit)
PWM2 :
bits : 25 - 25 (1 bit)
PWM3 :
bits : 26 - 26 (1 bit)
DPORT_PERIP_RST_EN
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIP_RST :
bits : 0 - 31 (32 bit)
SLAVE_SPI_MASK_PRO :
bits : 0 - 0 (1 bit)
TIMERS :
bits : 0 - 0 (1 bit)
SPI0 :
bits : 1 - 1 (1 bit)
UART0 :
bits : 2 - 2 (1 bit)
WDG :
bits : 3 - 3 (1 bit)
SLAVE_SPI_MASK_APP :
bits : 4 - 4 (1 bit)
I2S0 :
bits : 4 - 4 (1 bit)
UART1 :
bits : 5 - 5 (1 bit)
SPI2 :
bits : 6 - 6 (1 bit)
I2C0 :
bits : 7 - 7 (1 bit)
SPI_ENCRYPT_ENABLE :
bits : 8 - 8 (1 bit)
UHCI0 :
bits : 8 - 8 (1 bit)
REMOTE_CONTROLLER :
bits : 9 - 9 (1 bit)
PULSE_CNT :
bits : 10 - 10 (1 bit)
LED_PWM :
bits : 11 - 11 (1 bit)
SPI_DECRYPT_ENABLE :
bits : 12 - 12 (1 bit)
UHCI1 :
bits : 12 - 12 (1 bit)
TIMER_GROUP0 :
bits : 13 - 13 (1 bit)
EFUSE :
bits : 14 - 14 (1 bit)
TIMER_GROUP1 :
bits : 15 - 15 (1 bit)
SPI3 :
bits : 16 - 16 (1 bit)
PWM0 :
bits : 17 - 17 (1 bit)
I2C1 :
bits : 18 - 18 (1 bit)
CAN :
bits : 19 - 19 (1 bit)
PWM1 :
bits : 20 - 20 (1 bit)
I2S1 :
bits : 21 - 21 (1 bit)
SPI_DMA :
bits : 22 - 22 (1 bit)
UART2 :
bits : 23 - 23 (1 bit)
UART_MEM :
bits : 24 - 24 (1 bit)
PWM2 :
bits : 25 - 25 (1 bit)
PWM3 :
bits : 26 - 26 (1 bit)
DPORT_WIFI_CLK_EN
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIFI_CLK_EN :
bits : 0 - 31 (32 bit)
DPORT_CORE_RST_EN
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE_RST :
bits : 0 - 31 (32 bit)
DPORT_BT_LPCK_DIV_INT
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BT_LPCK_DIV_NUM :
bits : 0 - 11 (12 bit)
BTEXTWAKEUP_REQ :
bits : 12 - 12 (1 bit)
DPORT_BT_LPCK_DIV_FRAC
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BT_LPCK_DIV_B :
bits : 0 - 11 (12 bit)
BT_LPCK_DIV_A :
bits : 12 - 23 (12 bit)
LPCLK_SEL_RTC_SLOW :
bits : 24 - 24 (1 bit)
LPCLK_SEL_8M :
bits : 25 - 25 (1 bit)
LPCLK_SEL_XTAL :
bits : 26 - 26 (1 bit)
LPCLK_SEL_XTAL32K :
bits : 27 - 27 (1 bit)
DPORT_CPU_INTR_FROM_CPU_0
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INTR_FROM_CPU_0 :
bits : 0 - 0 (1 bit)
DPORT_CPU_INTR_FROM_CPU_1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INTR_FROM_CPU_1 :
bits : 0 - 0 (1 bit)
DPORT_CPU_INTR_FROM_CPU_2
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INTR_FROM_CPU_2 :
bits : 0 - 0 (1 bit)
DPORT_CPU_INTR_FROM_CPU_3
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INTR_FROM_CPU_3 :
bits : 0 - 0 (1 bit)
DPORT_PRO_INTR_STATUS_0
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_INTR_STATUS_0 :
bits : 0 - 31 (32 bit)
DPORT_PRO_INTR_STATUS_1
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_INTR_STATUS_1 :
bits : 0 - 31 (32 bit)
DPORT_PRO_INTR_STATUS_2
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRO_INTR_STATUS_2 :
bits : 0 - 31 (32 bit)
DPORT_APP_INTR_STATUS_0
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_INTR_STATUS_0 :
bits : 0 - 31 (32 bit)
DPORT_APP_INTR_STATUS_1
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APP_INTR_STATUS_1 :
bits : 0 - 31 (32 bit)
DPORT_DATE
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATE :
bits : 0 - 27 (28 bit)
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