\n

TIMG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x580 byte (0x0)
mem_usage : registers
protection : not protected

Registers

T0CONFIG

T0ALARMLO

T0ALARMHI

T0LOADLO

T0LOADHI

T0LOAD

T1CONFIG

T1LO

T1HI

T1UPDATE

T1ALARMLO

T1ALARMHI

T1LOADLO

T0LO

T1LOADHI

T1LOAD

WDTCONFIG0

WDTCONFIG1

WDTCONFIG2

WDTCONFIG3

WDTCONFIG4

WDTCONFIG5

WDTFEED

WDTWPROTECT

RTCCALICFG

RTCCALICFG1

LACTCONFIG

LACTRTC

LACTLO

LACTHI

T0HI

LACTUPDATE

LACTALARMLO

LACTALARMHI

LACTLOADLO

LACTLOADHI

LACTLOAD

INT_ENA_TIMERS

INT_RAW_TIMERS

INT_ST_TIMERS

INT_CLR_TIMERS

T0UPDATE

NTIMERS_DATE

TIMGCLK


T0CONFIG

TIMG_T0CONFIG
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0CONFIG T0CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_ALARM_EN T0_LEVEL_INT_EN T0_EDGE_INT_EN T0_DIVIDER T0_AUTORELOAD T0_INCREASE T0_EN

T0_ALARM_EN :
bits : 10 - 10 (1 bit)

T0_LEVEL_INT_EN :
bits : 11 - 11 (1 bit)

T0_EDGE_INT_EN :
bits : 12 - 12 (1 bit)

T0_DIVIDER :
bits : 13 - 28 (16 bit)

T0_AUTORELOAD :
bits : 29 - 29 (1 bit)

T0_INCREASE :
bits : 30 - 30 (1 bit)

T0_EN :
bits : 31 - 31 (1 bit)


T0ALARMLO

TIMG_T0ALARMLO
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0ALARMLO T0ALARMLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_ALARM_LO

T0_ALARM_LO :
bits : 0 - 31 (32 bit)


T0ALARMHI

TIMG_T0ALARMHI
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0ALARMHI T0ALARMHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_ALARM_HI

T0_ALARM_HI :
bits : 0 - 31 (32 bit)


T0LOADLO

TIMG_T0LOADLO
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0LOADLO T0LOADLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_LOAD_LO

T0_LOAD_LO :
bits : 0 - 31 (32 bit)


T0LOADHI

TIMG_T0LOADHI
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0LOADHI T0LOADHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_LOAD_HI

T0_LOAD_HI :
bits : 0 - 31 (32 bit)


T0LOAD

TIMG_T0LOAD
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0LOAD T0LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_LOAD

T0_LOAD :
bits : 0 - 31 (32 bit)


T1CONFIG

TIMG_T1CONFIG
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1CONFIG T1CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_ALARM_EN T1_LEVEL_INT_EN T1_EDGE_INT_EN T1_DIVIDER T1_AUTORELOAD T1_INCREASE T1_EN

T1_ALARM_EN :
bits : 10 - 10 (1 bit)

T1_LEVEL_INT_EN :
bits : 11 - 11 (1 bit)

T1_EDGE_INT_EN :
bits : 12 - 12 (1 bit)

T1_DIVIDER :
bits : 13 - 28 (16 bit)

T1_AUTORELOAD :
bits : 29 - 29 (1 bit)

T1_INCREASE :
bits : 30 - 30 (1 bit)

T1_EN :
bits : 31 - 31 (1 bit)


T1LO

TIMG_T1LO
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1LO T1LO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_LO

T1_LO :
bits : 0 - 31 (32 bit)


T1HI

TIMG_T1HI
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1HI T1HI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_HI

T1_HI :
bits : 0 - 31 (32 bit)


T1UPDATE

TIMG_T1UPDATE
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1UPDATE T1UPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_UPDATE

T1_UPDATE :
bits : 0 - 31 (32 bit)


T1ALARMLO

TIMG_T1ALARMLO
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1ALARMLO T1ALARMLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_ALARM_LO

T1_ALARM_LO :
bits : 0 - 31 (32 bit)


T1ALARMHI

TIMG_T1ALARMHI
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1ALARMHI T1ALARMHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_ALARM_HI

T1_ALARM_HI :
bits : 0 - 31 (32 bit)


T1LOADLO

TIMG_T1LOADLO
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1LOADLO T1LOADLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_LOAD_LO

T1_LOAD_LO :
bits : 0 - 31 (32 bit)


T0LO

TIMG_T0LO
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0LO T0LO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_LO

T0_LO :
bits : 0 - 31 (32 bit)


T1LOADHI

TIMG_T1LOADHI
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1LOADHI T1LOADHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_LOAD_HI

T1_LOAD_HI :
bits : 0 - 31 (32 bit)


T1LOAD

TIMG_T1LOAD
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1LOAD T1LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1_LOAD

T1_LOAD :
bits : 0 - 31 (32 bit)


WDTCONFIG0

TIMG_WDTCONFIG0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCONFIG0 WDTCONFIG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_FLASHBOOT_MOD_EN WDT_SYS_RESET_LENGTH WDT_CPU_RESET_LENGTH WDT_LEVEL_INT_EN WDT_EDGE_INT_EN WDT_STG3 WDT_STG2 WDT_STG1 WDT_STG0 WDT_EN

WDT_FLASHBOOT_MOD_EN :
bits : 14 - 14 (1 bit)

WDT_SYS_RESET_LENGTH :
bits : 15 - 17 (3 bit)

Enumeration:

End of enumeration elements list.

WDT_CPU_RESET_LENGTH :
bits : 18 - 20 (3 bit)

Enumeration: WDT_CPU_RESET_LENGTH ( read-write )

0 : T100ns

100ns

1 : T200ns

200ns

2 : T300ns

300ns

3 : T400ns

400ns

4 : T500ns

500ns

5 : T800ns

800ns

6 : T1600ns

1600ns

7 : T3200ns

3200ns

End of enumeration elements list.

WDT_LEVEL_INT_EN :
bits : 21 - 21 (1 bit)

WDT_EDGE_INT_EN :
bits : 22 - 22 (1 bit)

WDT_STG3 :
bits : 23 - 24 (2 bit)

Enumeration:

End of enumeration elements list.

WDT_STG2 :
bits : 25 - 26 (2 bit)

Enumeration:

End of enumeration elements list.

WDT_STG1 :
bits : 27 - 28 (2 bit)

Enumeration:

End of enumeration elements list.

WDT_STG0 :
bits : 29 - 30 (2 bit)

Enumeration: WDT_STG0 ( read-write )

0 : Disable

Disabled

1 : Interrupt

Trigger an interrupt

2 : ResetCPU

Reset CPU core

3 : ResetSystem

Reset System

End of enumeration elements list.

WDT_EN :
bits : 31 - 31 (1 bit)


WDTCONFIG1

TIMG_WDTCONFIG1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCONFIG1 WDTCONFIG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_CLK_PRESCALE

WDT_CLK_PRESCALE :
bits : 16 - 31 (16 bit)


WDTCONFIG2

TIMG_WDTCONFIG2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCONFIG2 WDTCONFIG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_STG0_HOLD

WDT_STG0_HOLD :
bits : 0 - 31 (32 bit)


WDTCONFIG3

TIMG_WDTCONFIG3
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCONFIG3 WDTCONFIG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_STG1_HOLD

WDT_STG1_HOLD :
bits : 0 - 31 (32 bit)


WDTCONFIG4

TIMG_WDTCONFIG4
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCONFIG4 WDTCONFIG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_STG2_HOLD

WDT_STG2_HOLD :
bits : 0 - 31 (32 bit)


WDTCONFIG5

TIMG_WDTCONFIG5
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCONFIG5 WDTCONFIG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_STG3_HOLD

WDT_STG3_HOLD :
bits : 0 - 31 (32 bit)


WDTFEED

TIMG_WDTFEED
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTFEED WDTFEED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_FEED

WDT_FEED :
bits : 0 - 31 (32 bit)


WDTWPROTECT

TIMG_WDTWPROTECT
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTWPROTECT WDTWPROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_WKEY

WDT_WKEY :
bits : 0 - 31 (32 bit)


RTCCALICFG

TIMG_RTCCALICFG
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCCALICFG RTCCALICFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLING CLK_SEL RDY MAX START

START_CYCLING :
bits : 12 - 12 (1 bit)

CLK_SEL :
bits : 13 - 14 (2 bit)

Enumeration: CLK_SEL ( read-write )

0 : RTC_MUX

Select RTC slow clock

1 : CK8M_D256

Internal 8 MHz RC oscillator, divided by 256

2 : XTAL32K

Select XTAL_32K

End of enumeration elements list.

RDY :
bits : 15 - 15 (1 bit)

MAX :
bits : 16 - 30 (15 bit)

START :
bits : 31 - 31 (1 bit)


RTCCALICFG1

TIMG_RTCCALICFG1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCCALICFG1 RTCCALICFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE :
bits : 7 - 31 (25 bit)


LACTCONFIG

TIMG_LACTCONFIG
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTCONFIG LACTCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_RTC_ONLY LACT_CPST_EN LACT_LAC_EN LACT_ALARM_EN LACT_LEVEL_INT_EN LACT_EDGE_INT_EN LACT_DIVIDER LACT_AUTORELOAD LACT_INCREASE LACT_EN

LACT_RTC_ONLY :
bits : 7 - 7 (1 bit)

LACT_CPST_EN :
bits : 8 - 8 (1 bit)

LACT_LAC_EN :
bits : 9 - 9 (1 bit)

LACT_ALARM_EN :
bits : 10 - 10 (1 bit)

LACT_LEVEL_INT_EN :
bits : 11 - 11 (1 bit)

LACT_EDGE_INT_EN :
bits : 12 - 12 (1 bit)

LACT_DIVIDER :
bits : 13 - 28 (16 bit)

LACT_AUTORELOAD :
bits : 29 - 29 (1 bit)

LACT_INCREASE :
bits : 30 - 30 (1 bit)

LACT_EN :
bits : 31 - 31 (1 bit)


LACTRTC

TIMG_LACTRTC
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTRTC LACTRTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_RTC_STEP_LEN

LACT_RTC_STEP_LEN :
bits : 6 - 31 (26 bit)


LACTLO

TIMG_LACTLO
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTLO LACTLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_LO

LACT_LO :
bits : 0 - 31 (32 bit)


LACTHI

TIMG_LACTHI
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTHI LACTHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_HI

LACT_HI :
bits : 0 - 31 (32 bit)


T0HI

TIMG_T0HI
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0HI T0HI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_HI

T0_HI :
bits : 0 - 31 (32 bit)


LACTUPDATE

TIMG_LACTUPDATE
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTUPDATE LACTUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_UPDATE

LACT_UPDATE :
bits : 0 - 31 (32 bit)


LACTALARMLO

TIMG_LACTALARMLO
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTALARMLO LACTALARMLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_ALARM_LO

LACT_ALARM_LO :
bits : 0 - 31 (32 bit)


LACTALARMHI

TIMG_LACTALARMHI
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTALARMHI LACTALARMHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_ALARM_HI

LACT_ALARM_HI :
bits : 0 - 31 (32 bit)


LACTLOADLO

TIMG_LACTLOADLO
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTLOADLO LACTLOADLO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_LOAD_LO

LACT_LOAD_LO :
bits : 0 - 31 (32 bit)


LACTLOADHI

TIMG_LACTLOADHI
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTLOADHI LACTLOADHI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_LOAD_HI

LACT_LOAD_HI :
bits : 0 - 31 (32 bit)


LACTLOAD

TIMG_LACTLOAD
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LACTLOAD LACTLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LACT_LOAD

LACT_LOAD :
bits : 0 - 31 (32 bit)


INT_ENA_TIMERS

TIMG_INT_ENA_TIMERS
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA_TIMERS INT_ENA_TIMERS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_INT_ENA T1_INT_ENA WDT_INT_ENA LACT_INT_ENA

T0_INT_ENA :
bits : 0 - 0 (1 bit)

T1_INT_ENA :
bits : 1 - 1 (1 bit)

WDT_INT_ENA :
bits : 2 - 2 (1 bit)

LACT_INT_ENA :
bits : 3 - 3 (1 bit)


INT_RAW_TIMERS

TIMG_INT_RAW_TIMERS
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW_TIMERS INT_RAW_TIMERS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_INT_RAW T1_INT_RAW WDT_INT_RAW LACT_INT_RAW

T0_INT_RAW :
bits : 0 - 0 (1 bit)

T1_INT_RAW :
bits : 1 - 1 (1 bit)

WDT_INT_RAW :
bits : 2 - 2 (1 bit)

LACT_INT_RAW :
bits : 3 - 3 (1 bit)


INT_ST_TIMERS

TIMG_INT_ST_TIMERS
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ST_TIMERS INT_ST_TIMERS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_INT_ST T1_INT_ST WDT_INT_ST LACT_INT_ST

T0_INT_ST :
bits : 0 - 0 (1 bit)

T1_INT_ST :
bits : 1 - 1 (1 bit)

WDT_INT_ST :
bits : 2 - 2 (1 bit)

LACT_INT_ST :
bits : 3 - 3 (1 bit)


INT_CLR_TIMERS

TIMG_INT_CLR_TIMERS
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR_TIMERS INT_CLR_TIMERS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_INT_CLR T1_INT_CLR WDT_INT_CLR LACT_INT_CLR

T0_INT_CLR :
bits : 0 - 0 (1 bit)

T1_INT_CLR :
bits : 1 - 1 (1 bit)

WDT_INT_CLR :
bits : 2 - 2 (1 bit)

LACT_INT_CLR :
bits : 3 - 3 (1 bit)


T0UPDATE

TIMG_T0UPDATE
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T0UPDATE T0UPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0_UPDATE

T0_UPDATE :
bits : 0 - 31 (32 bit)


NTIMERS_DATE

TIMG_NTIMERS_DATE
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NTIMERS_DATE NTIMERS_DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NTIMERS_DATE

NTIMERS_DATE :
bits : 0 - 27 (28 bit)


TIMGCLK

TIMGCLK
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMGCLK TIMGCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_EN

CLK_EN :
bits : 31 - 31 (1 bit)



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