\n
address_offset : 0x0 Bytes (0x0)
size : 0x0 byte (0x0)
mem_usage : registers
protection : not protected
configures clock source and clock output pins
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN_CTRL_CLK1 :
bits : 0 - 2 (3 bit)
PIN_CTRL_CLK2 :
bits : 4 - 6 (3 bit)
PIN_CTRL_CLK3 :
bits : 8 - 10 (3 bit)
configures IO_MUX for GPIO39
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO34
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures drive strength during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO35
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO32
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO33
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO25
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO26
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO27
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for MTMS
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for MTDI
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for MTCK
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for MTDO
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO36
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO16
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO17
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for SD_DATA2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for SD_DATA3
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for SD_CMD
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for SD_CLK
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for SD_DATA0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for SD_DATA1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO5
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO18
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO19
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO20
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO21
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO37
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO22
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for U0RXD
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for U0TXD
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO23
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO24
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
configures IO_MUX for GPIO38
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)
SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)
MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)
MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)
MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)
MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)
FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)
FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)
FUN_IE : configures input enable
bits : 9 - 9 (1 bit)
FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)
MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)
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