\n

IO_MUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PIN_CTRL

GPIO39

GPIO34

GPIO35

GPIO32

GPIO33

GPIO25

GPIO26

GPIO27

MTMS

MTDI

MTCK

MTDO

GPIO36

GPIO2

GPIO0

GPIO4

GPIO16

GPIO17

SD_DATA2

SD_DATA3

SD_CMD

SD_CLK

SD_DATA0

SD_DATA1

GPIO5

GPIO18

GPIO19

GPIO20

GPIO21

GPIO37

GPIO22

U0RXD

U0TXD

GPIO23

GPIO24

GPIO38


PIN_CTRL

configures clock source and clock output pins
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN_CTRL PIN_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN_CTRL_CLK1 PIN_CTRL_CLK2 PIN_CTRL_CLK3

PIN_CTRL_CLK1 :
bits : 0 - 2 (3 bit)

PIN_CTRL_CLK2 :
bits : 4 - 6 (3 bit)

PIN_CTRL_CLK3 :
bits : 8 - 10 (3 bit)


GPIO39

configures IO_MUX for GPIO39
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO39 GPIO39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO34

configures IO_MUX for GPIO34
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO34 GPIO34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures drive strength during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO35

configures IO_MUX for GPIO35
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO35 GPIO35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO32

configures IO_MUX for GPIO32
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO32 GPIO32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO33

configures IO_MUX for GPIO33
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO33 GPIO33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO25

configures IO_MUX for GPIO25
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO25 GPIO25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO26

configures IO_MUX for GPIO26
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO26 GPIO26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO27

configures IO_MUX for GPIO27
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO27 GPIO27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


MTMS

configures IO_MUX for MTMS
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTMS MTMS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


MTDI

configures IO_MUX for MTDI
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTDI MTDI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


MTCK

configures IO_MUX for MTCK
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTCK MTCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


MTDO

configures IO_MUX for MTDO
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTDO MTDO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO36

configures IO_MUX for GPIO36
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO36 GPIO36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO2

configures IO_MUX for GPIO2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO2 GPIO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO0

configures IO_MUX for GPIO0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO0 GPIO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO4

configures IO_MUX for GPIO4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO4 GPIO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO16

configures IO_MUX for GPIO16
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO16 GPIO16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO17

configures IO_MUX for GPIO17
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO17 GPIO17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


SD_DATA2

configures IO_MUX for SD_DATA2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SD_DATA2 SD_DATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


SD_DATA3

configures IO_MUX for SD_DATA3
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SD_DATA3 SD_DATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


SD_CMD

configures IO_MUX for SD_CMD
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SD_CMD SD_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


SD_CLK

configures IO_MUX for SD_CLK
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SD_CLK SD_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


SD_DATA0

configures IO_MUX for SD_DATA0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SD_DATA0 SD_DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


SD_DATA1

configures IO_MUX for SD_DATA1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SD_DATA1 SD_DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO5

configures IO_MUX for GPIO5
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO5 GPIO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO18

configures IO_MUX for GPIO18
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO18 GPIO18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO19

configures IO_MUX for GPIO19
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO19 GPIO19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO20

configures IO_MUX for GPIO20
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO20 GPIO20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO21

configures IO_MUX for GPIO21
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO21 GPIO21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO37

configures IO_MUX for GPIO37
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO37 GPIO37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO22

configures IO_MUX for GPIO22
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO22 GPIO22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


U0RXD

configures IO_MUX for U0RXD
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0RXD U0RXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


U0TXD

configures IO_MUX for U0TXD
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

U0TXD U0TXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO23

configures IO_MUX for GPIO23
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO23 GPIO23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO24

configures IO_MUX for GPIO24
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO24 GPIO24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)


GPIO38

configures IO_MUX for GPIO38
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO38 GPIO38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_OE SLP_SEL MCU_WPD MCU_WPU MCU_IE MCU_DRV FUN_WPD FUN_WPU FUN_IE FUN_DRV MCU_SEL

MCU_OE : configures output enable during sleep mode
bits : 0 - 0 (1 bit)

SLP_SEL : configures sleep mode selection
bits : 1 - 1 (1 bit)

MCU_WPD : configures pull down during sleep mode
bits : 2 - 2 (1 bit)

MCU_WPU : configures pull up during sleep mode
bits : 3 - 3 (1 bit)

MCU_IE : configures input enable during sleep mode
bits : 4 - 4 (1 bit)

MCU_DRV : configures drive strength during sleep mode
bits : 5 - 6 (2 bit)

FUN_WPD : configures pull down
bits : 7 - 7 (1 bit)

FUN_WPU : configures pull up
bits : 8 - 8 (1 bit)

FUN_IE : configures input enable
bits : 9 - 9 (1 bit)

FUN_DRV : configures drive strength
bits : 10 - 11 (2 bit)

MCU_SEL : configures IO_MUX function
bits : 12 - 13 (2 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.