\n

SYSCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x220 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSCLK_CONF

SARADC_CTRL

SARADC_CTRL2

SARADC_FSM

SARADC_SAR1_PATT_TAB1

SARADC_SAR1_PATT_TAB2

SARADC_SAR1_PATT_TAB3

SARADC_SAR1_PATT_TAB4

SARADC_SAR2_PATT_TAB1

SARADC_SAR2_PATT_TAB2

SARADC_SAR2_PATT_TAB3

SARADC_SAR2_PATT_TAB4

APLL_TICK_CONF

XTAL_TICK_CONF

DATE

PLL_TICK_CONF

CK8M_TICK_CONF


SYSCLK_CONF

SYSCON_SYSCLK_CONF
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCLK_CONF SYSCLK_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE_DIV_CNT CLK_320M_EN CLK_EN RST_TICK_CNT QUICK_CLK_CHNG

PRE_DIV_CNT :
bits : 0 - 9 (10 bit)

CLK_320M_EN :
bits : 10 - 10 (1 bit)

CLK_EN :
bits : 11 - 11 (1 bit)

RST_TICK_CNT :
bits : 12 - 12 (1 bit)

QUICK_CLK_CHNG :
bits : 13 - 13 (1 bit)


SARADC_CTRL

SYSCON_SARADC_CTRL
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_CTRL SARADC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_START_FORCE SARADC_START SARADC_SAR2_MUX SARADC_WORK_MODE SARADC_SAR_SEL SARADC_SAR_CLK_GATED SARADC_SAR_CLK_DIV SARADC_SAR1_PATT_LEN SARADC_SAR2_PATT_LEN SARADC_SAR1_PATT_P_CLEAR SARADC_SAR2_PATT_P_CLEAR SARADC_DATA_SAR_SEL SARADC_DATA_TO_I2S

SARADC_START_FORCE :
bits : 0 - 0 (1 bit)

SARADC_START :
bits : 1 - 1 (1 bit)

SARADC_SAR2_MUX :
bits : 2 - 2 (1 bit)

SARADC_WORK_MODE :
bits : 3 - 4 (2 bit)

SARADC_SAR_SEL :
bits : 5 - 5 (1 bit)

SARADC_SAR_CLK_GATED :
bits : 6 - 6 (1 bit)

SARADC_SAR_CLK_DIV :
bits : 7 - 14 (8 bit)

SARADC_SAR1_PATT_LEN :
bits : 15 - 18 (4 bit)

SARADC_SAR2_PATT_LEN :
bits : 19 - 22 (4 bit)

SARADC_SAR1_PATT_P_CLEAR :
bits : 23 - 23 (1 bit)

SARADC_SAR2_PATT_P_CLEAR :
bits : 24 - 24 (1 bit)

SARADC_DATA_SAR_SEL :
bits : 25 - 25 (1 bit)

SARADC_DATA_TO_I2S :
bits : 26 - 26 (1 bit)


SARADC_CTRL2

SYSCON_SARADC_CTRL2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_CTRL2 SARADC_CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_MEAS_NUM_LIMIT SARADC_MAX_MEAS_NUM SARADC_SAR1_INV SARADC_SAR2_INV

SARADC_MEAS_NUM_LIMIT :
bits : 0 - 0 (1 bit)

SARADC_MAX_MEAS_NUM :
bits : 1 - 8 (8 bit)

SARADC_SAR1_INV :
bits : 9 - 9 (1 bit)

SARADC_SAR2_INV :
bits : 10 - 10 (1 bit)


SARADC_FSM

SYSCON_SARADC_FSM
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_FSM SARADC_FSM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_RSTB_WAIT SARADC_STANDBY_WAIT SARADC_START_WAIT SARADC_SAMPLE_CYCLE

SARADC_RSTB_WAIT :
bits : 0 - 7 (8 bit)

SARADC_STANDBY_WAIT :
bits : 8 - 15 (8 bit)

SARADC_START_WAIT :
bits : 16 - 23 (8 bit)

SARADC_SAMPLE_CYCLE :
bits : 24 - 31 (8 bit)


SARADC_SAR1_PATT_TAB1

SYSCON_SARADC_SAR1_PATT_TAB1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR1_PATT_TAB1 SARADC_SAR1_PATT_TAB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR1_PATT_TAB1

SARADC_SAR1_PATT_TAB1 :
bits : 0 - 31 (32 bit)


SARADC_SAR1_PATT_TAB2

SYSCON_SARADC_SAR1_PATT_TAB2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR1_PATT_TAB2 SARADC_SAR1_PATT_TAB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR1_PATT_TAB2

SARADC_SAR1_PATT_TAB2 :
bits : 0 - 31 (32 bit)


SARADC_SAR1_PATT_TAB3

SYSCON_SARADC_SAR1_PATT_TAB3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR1_PATT_TAB3 SARADC_SAR1_PATT_TAB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR1_PATT_TAB3

SARADC_SAR1_PATT_TAB3 :
bits : 0 - 31 (32 bit)


SARADC_SAR1_PATT_TAB4

SYSCON_SARADC_SAR1_PATT_TAB4
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR1_PATT_TAB4 SARADC_SAR1_PATT_TAB4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR1_PATT_TAB4

SARADC_SAR1_PATT_TAB4 :
bits : 0 - 31 (32 bit)


SARADC_SAR2_PATT_TAB1

SYSCON_SARADC_SAR2_PATT_TAB1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR2_PATT_TAB1 SARADC_SAR2_PATT_TAB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR2_PATT_TAB1

SARADC_SAR2_PATT_TAB1 :
bits : 0 - 31 (32 bit)


SARADC_SAR2_PATT_TAB2

SYSCON_SARADC_SAR2_PATT_TAB2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR2_PATT_TAB2 SARADC_SAR2_PATT_TAB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR2_PATT_TAB2

SARADC_SAR2_PATT_TAB2 :
bits : 0 - 31 (32 bit)


SARADC_SAR2_PATT_TAB3

SYSCON_SARADC_SAR2_PATT_TAB3
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR2_PATT_TAB3 SARADC_SAR2_PATT_TAB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR2_PATT_TAB3

SARADC_SAR2_PATT_TAB3 :
bits : 0 - 31 (32 bit)


SARADC_SAR2_PATT_TAB4

SYSCON_SARADC_SAR2_PATT_TAB4
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARADC_SAR2_PATT_TAB4 SARADC_SAR2_PATT_TAB4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SARADC_SAR2_PATT_TAB4

SARADC_SAR2_PATT_TAB4 :
bits : 0 - 31 (32 bit)


APLL_TICK_CONF

SYSCON_APLL_TICK_CONF
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLL_TICK_CONF APLL_TICK_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APLL_TICK_NUM

APLL_TICK_NUM :
bits : 0 - 7 (8 bit)


XTAL_TICK_CONF

SYSCON_XTAL_TICK_CONF
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL_TICK_CONF XTAL_TICK_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_TICK_NUM

XTAL_TICK_NUM :
bits : 0 - 7 (8 bit)


DATE

SYSCON_DATE
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 31 (32 bit)


PLL_TICK_CONF

SYSCON_PLL_TICK_CONF
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_TICK_CONF PLL_TICK_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_TICK_NUM

PLL_TICK_NUM :
bits : 0 - 7 (8 bit)


CK8M_TICK_CONF

SYSCON_CK8M_TICK_CONF
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CK8M_TICK_CONF CK8M_TICK_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CK8M_TICK_NUM

CK8M_TICK_NUM :
bits : 0 - 7 (8 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.