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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : UART registers
protection : not protected

address_offset : 0x200C0000 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : TX FIFO
protection : not protected

Registers

RX_FIFO

INT_CLR

CLKDIV

AUTOBAUD

STATUS

CONF0

TX_FIFO

CONF1

LOWPULSE

HIGHPULSE

RXD_CNT

FLOW_CONF

SLEEP_CONF

SWFC_CONF

INT_RAW

IDLE_CONF

RS485_CONF

AT_CMD_PRECNT

AT_CMD_POSTCNT

AT_CMD_GAPTOUT

AT_CMD_CHAR

MEM_CONF

MEM_TX_STATUS

MEM_RX_STATUS

MEM_CNT_STATUS

POSPULSE

NEGPULSE

DATE

ID

INT_ST

INT_ENA


RX_FIFO

UART_RX_FIFO
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_FIFO RX_FIFO read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : TX FIFO Data
bits : 0 - 7 (8 bit)


INT_CLR

UART_INT_CLR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_CLR TXFIFO_EMPTY_INT_CLR PARITY_ERR_INT_CLR FRM_ERR_INT_CLR RXFIFO_OVF_INT_CLR DSR_CHG_INT_CLR CTS_CHG_INT_CLR BRK_DET_INT_CLR RXFIFO_TOUT_INT_CLR SW_XON_INT_CLR SW_XOFF_INT_CLR GLITCH_DET_INT_CLR TX_BRK_DONE_INT_CLR TX_BRK_IDLE_DONE_INT_CLR TX_DONE_INT_CLR RS485_PARITY_ERR_INT_CLR RS485_FRM_ERR_INT_CLR RS485_CLASH_INT_CLR AT_CMD_CHAR_DET_INT_CLR

RXFIFO_FULL_INT_CLR :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_CLR :
bits : 1 - 1 (1 bit)

PARITY_ERR_INT_CLR :
bits : 2 - 2 (1 bit)

FRM_ERR_INT_CLR :
bits : 3 - 3 (1 bit)

RXFIFO_OVF_INT_CLR :
bits : 4 - 4 (1 bit)

DSR_CHG_INT_CLR :
bits : 5 - 5 (1 bit)

CTS_CHG_INT_CLR :
bits : 6 - 6 (1 bit)

BRK_DET_INT_CLR :
bits : 7 - 7 (1 bit)

RXFIFO_TOUT_INT_CLR :
bits : 8 - 8 (1 bit)

SW_XON_INT_CLR :
bits : 9 - 9 (1 bit)

SW_XOFF_INT_CLR :
bits : 10 - 10 (1 bit)

GLITCH_DET_INT_CLR :
bits : 11 - 11 (1 bit)

TX_BRK_DONE_INT_CLR :
bits : 12 - 12 (1 bit)

TX_BRK_IDLE_DONE_INT_CLR :
bits : 13 - 13 (1 bit)

TX_DONE_INT_CLR :
bits : 14 - 14 (1 bit)

RS485_PARITY_ERR_INT_CLR :
bits : 15 - 15 (1 bit)

RS485_FRM_ERR_INT_CLR :
bits : 16 - 16 (1 bit)

RS485_CLASH_INT_CLR :
bits : 17 - 17 (1 bit)

AT_CMD_CHAR_DET_INT_CLR :
bits : 18 - 18 (1 bit)


CLKDIV

UART_CLKDIV
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV CLKDIV_FRAG

CLKDIV :
bits : 0 - 19 (20 bit)

CLKDIV_FRAG :
bits : 20 - 23 (4 bit)


AUTOBAUD

UART_AUTOBAUD
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTOBAUD AUTOBAUD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOBAUD_EN GLITCH_FILT

AUTOBAUD_EN :
bits : 0 - 0 (1 bit)

GLITCH_FILT :
bits : 8 - 15 (8 bit)


STATUS

UART_STATUS
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_CNT ST_URX_OUT DSRN CTSN RXD TXFIFO_CNT ST_UTX_OUT DTRN RTSN TXD

RXFIFO_CNT :
bits : 0 - 7 (8 bit)

ST_URX_OUT :
bits : 8 - 11 (4 bit)

Enumeration: UART_ST_URX_OUT ( read-write )

0 : RX_IDLE

RX_IDLE

1 : RX_STRT

RX_STRT

2 : RX_DAT0

RX_DAT0

3 : RX_DAT1

RX_DAT1

4 : RX_DAT2

RX_DAT2

5 : RX_DAT3

RX_DAT3

6 : RX_DAT4

RX_DAT4

7 : RX_DAT5

RX_DAT5

8 : RX_DAT6

RX_DAT6

9 : RX_DAT7

RX_DAT7

10 : RX_PRTY

RX_PRTY

11 : RX_STP1

RX_STP1

12 : RX_STP2

RX_STP2

13 : RX_DL1

RX_DL1

End of enumeration elements list.

DSRN :
bits : 13 - 13 (1 bit)

CTSN :
bits : 14 - 14 (1 bit)

RXD :
bits : 15 - 15 (1 bit)

TXFIFO_CNT :
bits : 16 - 23 (8 bit)

ST_UTX_OUT :
bits : 24 - 27 (4 bit)

Enumeration: UART_ST_UTX_OUT ( read-write )

0 : TX_IDLE

TX_IDLE

1 : TX_STRT

TX_STRT

2 : TX_DAT0

TX_DAT0

3 : TX_DAT1

TX_DAT1

4 : TX_DAT2

TX_DAT2

5 : TX_DAT3

TX_DAT3

6 : TX_DAT4

TX_DAT4

7 : TX_DAT5

TX_DAT5

8 : TX_DAT6

TX_DAT6

9 : TX_DAT7

TX_DAT7

10 : TX_PRTY

TX_PRTY

11 : TX_STP1

TX_STP1

12 : TX_STP2

TX_STP2

14 : TX_DL1

TX_DL1

End of enumeration elements list.

DTRN :
bits : 29 - 29 (1 bit)

RTSN :
bits : 30 - 30 (1 bit)

TXD :
bits : 31 - 31 (1 bit)


CONF0

UART_CONF0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF0 CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARITY PARITY_EN BIT_NUM STOP_BIT_NUM SW_RTS SW_DTR TXD_BRK IRDA_DPLX IRDA_TX_EN IRDA_WCTL IRDA_TX_INV IRDA_RX_INV LOOPBACK TX_FLOW_EN IRDA_EN RXFIFO_RST TXFIFO_RST RXD_INV CTS_INV DSR_INV TXD_INV RTS_INV DTR_INV CLK_EN ERR_WR_MASK TICK_REF_ALWAYS_ON

PARITY :
bits : 0 - 0 (1 bit)

PARITY_EN :
bits : 1 - 1 (1 bit)

BIT_NUM :
bits : 2 - 3 (2 bit)

Enumeration: UART_BIT_NUM ( read-write )

0 : DATA_BITS_5

5 data bits

1 : DATA_BITS_6

6 data bits

2 : DATA_BITS_7

7 data bits

3 : DATA_BITS_8

8 data bits

End of enumeration elements list.

STOP_BIT_NUM :
bits : 4 - 5 (2 bit)

Enumeration: UART_STOP_BIT_NUM ( read-write )

1 : STOP_BITS_1

1 stop bits

2 : STOP_BITS_1p5

1.5 stop bits

3 : STOP_BITS_2

2 stop bits

End of enumeration elements list.

SW_RTS :
bits : 6 - 6 (1 bit)

SW_DTR :
bits : 7 - 7 (1 bit)

TXD_BRK :
bits : 8 - 8 (1 bit)

IRDA_DPLX :
bits : 9 - 9 (1 bit)

IRDA_TX_EN :
bits : 10 - 10 (1 bit)

IRDA_WCTL :
bits : 11 - 11 (1 bit)

IRDA_TX_INV :
bits : 12 - 12 (1 bit)

IRDA_RX_INV :
bits : 13 - 13 (1 bit)

LOOPBACK :
bits : 14 - 14 (1 bit)

TX_FLOW_EN :
bits : 15 - 15 (1 bit)

IRDA_EN :
bits : 16 - 16 (1 bit)

RXFIFO_RST :
bits : 17 - 17 (1 bit)

TXFIFO_RST :
bits : 18 - 18 (1 bit)

RXD_INV :
bits : 19 - 19 (1 bit)

CTS_INV :
bits : 20 - 20 (1 bit)

DSR_INV :
bits : 21 - 21 (1 bit)

TXD_INV :
bits : 22 - 22 (1 bit)

RTS_INV :
bits : 23 - 23 (1 bit)

DTR_INV :
bits : 24 - 24 (1 bit)

CLK_EN :
bits : 25 - 25 (1 bit)

ERR_WR_MASK :
bits : 26 - 26 (1 bit)

TICK_REF_ALWAYS_ON :
bits : 27 - 27 (1 bit)


TX_FIFO

UART_TX_FIFO
address_offset : 0x200C0000 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TX_FIFO TX_FIFO write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : TX FIFO Data
bits : 0 - 7 (8 bit)


CONF1

UART_CONF1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF1 CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_THRHD TXFIFO_EMPTY_THRHD RX_FLOW_THRHD RX_FLOW_EN RX_TOUT_THRHD RX_TOUT_EN

RXFIFO_FULL_THRHD :
bits : 0 - 6 (7 bit)

TXFIFO_EMPTY_THRHD :
bits : 8 - 14 (7 bit)

RX_FLOW_THRHD :
bits : 16 - 22 (7 bit)

RX_FLOW_EN :
bits : 23 - 23 (1 bit)

RX_TOUT_THRHD :
bits : 24 - 30 (7 bit)

RX_TOUT_EN :
bits : 31 - 31 (1 bit)


LOWPULSE

UART_LOWPULSE
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOWPULSE LOWPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWPULSE_MIN_CNT

LOWPULSE_MIN_CNT :
bits : 0 - 19 (20 bit)


HIGHPULSE

UART_HIGHPULSE
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIGHPULSE HIGHPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIGHPULSE_MIN_CNT

HIGHPULSE_MIN_CNT :
bits : 0 - 19 (20 bit)


RXD_CNT

UART_RXD_CNT
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD_CNT RXD_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXD_EDGE_CNT

RXD_EDGE_CNT :
bits : 0 - 9 (10 bit)


FLOW_CONF

UART_FLOW_CONF
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLOW_CONF FLOW_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_FLOW_CON_EN XONOFF_DEL FORCE_XON FORCE_XOFF SEND_XON SEND_XOFF

SW_FLOW_CON_EN :
bits : 0 - 0 (1 bit)

XONOFF_DEL :
bits : 1 - 1 (1 bit)

FORCE_XON :
bits : 2 - 2 (1 bit)

FORCE_XOFF :
bits : 3 - 3 (1 bit)

SEND_XON :
bits : 4 - 4 (1 bit)

SEND_XOFF :
bits : 5 - 5 (1 bit)


SLEEP_CONF

UART_SLEEP_CONF
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEP_CONF SLEEP_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE_THRESHOLD

ACTIVE_THRESHOLD :
bits : 0 - 9 (10 bit)


SWFC_CONF

UART_SWFC_CONF
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWFC_CONF SWFC_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XON_THRESHOLD XOFF_THRESHOLD XON_CHAR XOFF_CHAR

XON_THRESHOLD :
bits : 0 - 7 (8 bit)

XOFF_THRESHOLD :
bits : 8 - 15 (8 bit)

XON_CHAR :
bits : 16 - 23 (8 bit)

XOFF_CHAR :
bits : 24 - 31 (8 bit)


INT_RAW

UART_INT_RAW
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_RAW TXFIFO_EMPTY_INT_RAW PARITY_ERR_INT_RAW FRM_ERR_INT_RAW RXFIFO_OVF_INT_RAW DSR_CHG_INT_RAW CTS_CHG_INT_RAW BRK_DET_INT_RAW RXFIFO_TOUT_INT_RAW SW_XON_INT_RAW SW_XOFF_INT_RAW GLITCH_DET_INT_RAW TX_BRK_DONE_INT_RAW TX_BRK_IDLE_DONE_INT_RAW TX_DONE_INT_RAW RS485_PARITY_ERR_INT_RAW RS485_FRM_ERR_INT_RAW RS485_CLASH_INT_RAW AT_CMD_CHAR_DET_INT_RAW

RXFIFO_FULL_INT_RAW :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_RAW :
bits : 1 - 1 (1 bit)

PARITY_ERR_INT_RAW :
bits : 2 - 2 (1 bit)

FRM_ERR_INT_RAW :
bits : 3 - 3 (1 bit)

RXFIFO_OVF_INT_RAW :
bits : 4 - 4 (1 bit)

DSR_CHG_INT_RAW :
bits : 5 - 5 (1 bit)

CTS_CHG_INT_RAW :
bits : 6 - 6 (1 bit)

BRK_DET_INT_RAW :
bits : 7 - 7 (1 bit)

RXFIFO_TOUT_INT_RAW :
bits : 8 - 8 (1 bit)

SW_XON_INT_RAW :
bits : 9 - 9 (1 bit)

SW_XOFF_INT_RAW :
bits : 10 - 10 (1 bit)

GLITCH_DET_INT_RAW :
bits : 11 - 11 (1 bit)

TX_BRK_DONE_INT_RAW :
bits : 12 - 12 (1 bit)

TX_BRK_IDLE_DONE_INT_RAW :
bits : 13 - 13 (1 bit)

TX_DONE_INT_RAW :
bits : 14 - 14 (1 bit)

RS485_PARITY_ERR_INT_RAW :
bits : 15 - 15 (1 bit)

RS485_FRM_ERR_INT_RAW :
bits : 16 - 16 (1 bit)

RS485_CLASH_INT_RAW :
bits : 17 - 17 (1 bit)

AT_CMD_CHAR_DET_INT_RAW :
bits : 18 - 18 (1 bit)


IDLE_CONF

UART_IDLE_CONF
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDLE_CONF IDLE_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_IDLE_THRHD TX_IDLE_NUM TX_BRK_NUM

RX_IDLE_THRHD :
bits : 0 - 9 (10 bit)

TX_IDLE_NUM :
bits : 10 - 19 (10 bit)

TX_BRK_NUM :
bits : 20 - 27 (8 bit)


RS485_CONF

UART_RS485_CONF
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS485_CONF RS485_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS485_EN DL0_EN DL1_EN RS485TX_RX_EN RS485RXBY_TX_EN RS485_RX_DLY_NUM RS485_TX_DLY_NUM

RS485_EN :
bits : 0 - 0 (1 bit)

DL0_EN :
bits : 1 - 1 (1 bit)

DL1_EN :
bits : 2 - 2 (1 bit)

RS485TX_RX_EN :
bits : 3 - 3 (1 bit)

RS485RXBY_TX_EN :
bits : 4 - 4 (1 bit)

RS485_RX_DLY_NUM :
bits : 5 - 5 (1 bit)

RS485_TX_DLY_NUM :
bits : 6 - 9 (4 bit)


AT_CMD_PRECNT

UART_AT_CMD_PRECNT
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AT_CMD_PRECNT AT_CMD_PRECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE_IDLE_NUM

PRE_IDLE_NUM :
bits : 0 - 23 (24 bit)


AT_CMD_POSTCNT

UART_AT_CMD_POSTCNT
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AT_CMD_POSTCNT AT_CMD_POSTCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POST_IDLE_NUM

POST_IDLE_NUM :
bits : 0 - 23 (24 bit)


AT_CMD_GAPTOUT

UART_AT_CMD_GAPTOUT
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AT_CMD_GAPTOUT AT_CMD_GAPTOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_GAP_TOUT

RX_GAP_TOUT :
bits : 0 - 23 (24 bit)


AT_CMD_CHAR

UART_AT_CMD_CHAR
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AT_CMD_CHAR AT_CMD_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AT_CMD_CHAR CHAR_NUM

AT_CMD_CHAR :
bits : 0 - 7 (8 bit)

CHAR_NUM :
bits : 8 - 15 (8 bit)


MEM_CONF

UART_MEM_CONF
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_CONF MEM_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_PD RX_SIZE TX_SIZE RX_FLOW_THRHD_H3 RX_TOUT_THRHD_H3 XON_THRESHOLD_H2 XOFF_THRESHOLD_H2 RX_MEM_FULL_THRHD TX_MEM_EMPTY_THRHD

MEM_PD :
bits : 0 - 0 (1 bit)

RX_SIZE :
bits : 3 - 6 (4 bit)

TX_SIZE :
bits : 7 - 10 (4 bit)

RX_FLOW_THRHD_H3 :
bits : 15 - 17 (3 bit)

RX_TOUT_THRHD_H3 :
bits : 18 - 20 (3 bit)

XON_THRESHOLD_H2 :
bits : 21 - 22 (2 bit)

XOFF_THRESHOLD_H2 :
bits : 23 - 24 (2 bit)

RX_MEM_FULL_THRHD :
bits : 25 - 27 (3 bit)

TX_MEM_EMPTY_THRHD :
bits : 28 - 30 (3 bit)


MEM_TX_STATUS

UART_MEM_TX_STATUS
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_TX_STATUS MEM_TX_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_TX_STATUS

MEM_TX_STATUS :
bits : 0 - 23 (24 bit)


MEM_RX_STATUS

UART_MEM_RX_STATUS
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_RX_STATUS MEM_RX_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_RX_STATUS MEM_RX_RD_ADDR MEM_RX_WR_ADDR

MEM_RX_STATUS :
bits : 0 - 23 (24 bit)

MEM_RX_RD_ADDR :
bits : 2 - 12 (11 bit)

MEM_RX_WR_ADDR :
bits : 13 - 23 (11 bit)


MEM_CNT_STATUS

UART_MEM_CNT_STATUS
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_CNT_STATUS MEM_CNT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_MEM_CNT TX_MEM_CNT

RX_MEM_CNT :
bits : 0 - 2 (3 bit)

TX_MEM_CNT :
bits : 3 - 5 (3 bit)


POSPULSE

UART_POSPULSE
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POSPULSE POSPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSEDGE_MIN_CNT

POSEDGE_MIN_CNT :
bits : 0 - 19 (20 bit)


NEGPULSE

UART_NEGPULSE
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NEGPULSE NEGPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEGEDGE_MIN_CNT

NEGEDGE_MIN_CNT :
bits : 0 - 19 (20 bit)


DATE

UART_DATE
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 31 (32 bit)


ID

UART_ID
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID :
bits : 0 - 31 (32 bit)


INT_ST

UART_INT_ST
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ST INT_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_ST TXFIFO_EMPTY_INT_ST PARITY_ERR_INT_ST FRM_ERR_INT_ST RXFIFO_OVF_INT_ST DSR_CHG_INT_ST CTS_CHG_INT_ST BRK_DET_INT_ST RXFIFO_TOUT_INT_ST SW_XON_INT_ST SW_XOFF_INT_ST GLITCH_DET_INT_ST TX_BRK_DONE_INT_ST TX_BRK_IDLE_DONE_INT_ST TX_DONE_INT_ST RS485_PARITY_ERR_INT_ST RS485_FRM_ERR_INT_ST RS485_CLASH_INT_ST AT_CMD_CHAR_DET_INT_ST

RXFIFO_FULL_INT_ST :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_ST :
bits : 1 - 1 (1 bit)

PARITY_ERR_INT_ST :
bits : 2 - 2 (1 bit)

FRM_ERR_INT_ST :
bits : 3 - 3 (1 bit)

RXFIFO_OVF_INT_ST :
bits : 4 - 4 (1 bit)

DSR_CHG_INT_ST :
bits : 5 - 5 (1 bit)

CTS_CHG_INT_ST :
bits : 6 - 6 (1 bit)

BRK_DET_INT_ST :
bits : 7 - 7 (1 bit)

RXFIFO_TOUT_INT_ST :
bits : 8 - 8 (1 bit)

SW_XON_INT_ST :
bits : 9 - 9 (1 bit)

SW_XOFF_INT_ST :
bits : 10 - 10 (1 bit)

GLITCH_DET_INT_ST :
bits : 11 - 11 (1 bit)

TX_BRK_DONE_INT_ST :
bits : 12 - 12 (1 bit)

TX_BRK_IDLE_DONE_INT_ST :
bits : 13 - 13 (1 bit)

TX_DONE_INT_ST :
bits : 14 - 14 (1 bit)

RS485_PARITY_ERR_INT_ST :
bits : 15 - 15 (1 bit)

RS485_FRM_ERR_INT_ST :
bits : 16 - 16 (1 bit)

RS485_CLASH_INT_ST :
bits : 17 - 17 (1 bit)

AT_CMD_CHAR_DET_INT_ST :
bits : 18 - 18 (1 bit)


INT_ENA

UART_INT_ENA
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_ENA TXFIFO_EMPTY_INT_ENA PARITY_ERR_INT_ENA FRM_ERR_INT_ENA RXFIFO_OVF_INT_ENA DSR_CHG_INT_ENA CTS_CHG_INT_ENA BRK_DET_INT_ENA RXFIFO_TOUT_INT_ENA SW_XON_INT_ENA SW_XOFF_INT_ENA GLITCH_DET_INT_ENA TX_BRK_DONE_INT_ENA TX_BRK_IDLE_DONE_INT_ENA TX_DONE_INT_ENA RS485_PARITY_ERR_INT_ENA RS485_FRM_ERR_INT_ENA RS485_CLASH_INT_ENA AT_CMD_CHAR_DET_INT_ENA

RXFIFO_FULL_INT_ENA :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_ENA :
bits : 1 - 1 (1 bit)

PARITY_ERR_INT_ENA :
bits : 2 - 2 (1 bit)

FRM_ERR_INT_ENA :
bits : 3 - 3 (1 bit)

RXFIFO_OVF_INT_ENA :
bits : 4 - 4 (1 bit)

DSR_CHG_INT_ENA :
bits : 5 - 5 (1 bit)

CTS_CHG_INT_ENA :
bits : 6 - 6 (1 bit)

BRK_DET_INT_ENA :
bits : 7 - 7 (1 bit)

RXFIFO_TOUT_INT_ENA :
bits : 8 - 8 (1 bit)

SW_XON_INT_ENA :
bits : 9 - 9 (1 bit)

SW_XOFF_INT_ENA :
bits : 10 - 10 (1 bit)

GLITCH_DET_INT_ENA :
bits : 11 - 11 (1 bit)

TX_BRK_DONE_INT_ENA :
bits : 12 - 12 (1 bit)

TX_BRK_IDLE_DONE_INT_ENA :
bits : 13 - 13 (1 bit)

TX_DONE_INT_ENA :
bits : 14 - 14 (1 bit)

RS485_PARITY_ERR_INT_ENA :
bits : 15 - 15 (1 bit)

RS485_FRM_ERR_INT_ENA :
bits : 16 - 16 (1 bit)

RS485_CLASH_INT_ENA :
bits : 17 - 17 (1 bit)

AT_CMD_CHAR_DET_INT_ENA :
bits : 18 - 18 (1 bit)



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