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MCPWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x940 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_CFG

TIMER0_STATUS

CAP_CH1

CAP_CH2

CAP_STATUS

UPDATE_CFG

MCMCPWM_INT_ENA_MCPWM

MCMCPWM_INT_RAW_MCPWM

MCMCPWM_INT_ST_MCPWM

MCMCPWM_INT_CLR_MCPWM

CLK

VERSION

TIMER1_CFG0

TIMER1_CFG1

TIMER1_SYNC

TIMER1_STATUS

TIMER2_CFG0

TIMER2_CFG1

TIMER2_SYNC

TIMER2_STATUS

TIMER_SYNCI_CFG

OPERATOR_TIMERSEL

GEN0_STMP_CFG

TIMER0_CFG0

GEN0_TSTMP_A

GEN0_TSTMP_B

GEN0_CFG0

GEN0_FORCE

GEN0_A

GEN0_B

DT0_CFG

DT0_FED_CFG

DT0_RED_CFG

CARRIER0_CFG

FH0_CFG0

FH0_CFG1

FH0_STATUS

GEN1_STMP_CFG

GEN1_TSTMP_A

GEN1_TSTMP_B

TIMER0_CFG1

GEN1_CFG0

GEN1_FORCE

GEN1_A

GEN1_B

DT1_CFG

DT1_FED_CFG

DT1_RED_CFG

CARRIER1_CFG

FH1_CFG0

FH1_CFG1

FH1_STATUS

GEN2_STMP_CFG

GEN2_TSTMP_A

GEN2_TSTMP_B

GEN2_CFG0

GEN2_FORCE

TIMER0_SYNC

GEN2_A

GEN2_B

DT2_CFG

DT2_FED_CFG

DT2_RED_CFG

CARRIER2_CFG

FH2_CFG0

FH2_CFG1

FH2_STATUS

FAULT_DETECT

CAP_TIMER_CFG

CAP_TIMER_PHASE

CAP_CH0_CFG

CAP_CH1_CFG

CAP_CH2_CFG

CAP_CH0


CLK_CFG

MCPWM_CLK_CFG
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CFG CLK_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_PRESCALE

CLK_PRESCALE :
bits : 0 - 7 (8 bit)


TIMER0_STATUS

MCPWM_TIMER0_STATUS
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_STATUS TIMER0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_VALUE TIMER0_DIRECTION

TIMER0_VALUE :
bits : 0 - 15 (16 bit)

TIMER0_DIRECTION :
bits : 16 - 16 (1 bit)


CAP_CH1

MCPWM_CAP_CH1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_CH1 CAP_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP1_VALUE

CAP1_VALUE :
bits : 0 - 31 (32 bit)


CAP_CH2

MCPWM_CAP_CH2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_CH2 CAP_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP2_VALUE

CAP2_VALUE :
bits : 0 - 31 (32 bit)


CAP_STATUS

MCPWM_CAP_STATUS
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_STATUS CAP_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_EDGE CAP1_EDGE CAP2_EDGE

CAP0_EDGE :
bits : 0 - 0 (1 bit)

CAP1_EDGE :
bits : 1 - 1 (1 bit)

CAP2_EDGE :
bits : 2 - 2 (1 bit)


UPDATE_CFG

MCPWM_UPDATE_CFG
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPDATE_CFG UPDATE_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLOBAL_UP_EN GLOBAL_FORCE_UP OP0_UP_EN OP0_FORCE_UP OP1_UP_EN OP1_FORCE_UP OP2_UP_EN OP2_FORCE_UP

GLOBAL_UP_EN :
bits : 0 - 0 (1 bit)

GLOBAL_FORCE_UP :
bits : 1 - 1 (1 bit)

OP0_UP_EN :
bits : 2 - 2 (1 bit)

OP0_FORCE_UP :
bits : 3 - 3 (1 bit)

OP1_UP_EN :
bits : 4 - 4 (1 bit)

OP1_FORCE_UP :
bits : 5 - 5 (1 bit)

OP2_UP_EN :
bits : 6 - 6 (1 bit)

OP2_FORCE_UP :
bits : 7 - 7 (1 bit)


MCMCPWM_INT_ENA_MCPWM

MCMCPWM_INT_ENA_MCPWM
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMCPWM_INT_ENA_MCPWM MCMCPWM_INT_ENA_MCPWM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_STOP_INT_ENA TIMER1_STOP_INT_ENA TIMER2_STOP_INT_ENA TIMER0_TEZ_INT_ENA TIMER1_TEZ_INT_ENA TIMER2_TEZ_INT_ENA TIMER0_TEP_INT_ENA TIMER1_TEP_INT_ENA TIMER2_TEP_INT_ENA FAULT0_INT_ENA FAULT1_INT_ENA FAULT2_INT_ENA FAULT0_CLR_INT_ENA FAULT1_CLR_INT_ENA FAULT2_CLR_INT_ENA OP0_TEA_INT_ENA OP1_TEA_INT_ENA OP2_TEA_INT_ENA OP0_TEB_INT_ENA OP1_TEB_INT_ENA OP2_TEB_INT_ENA FH0_CBC_INT_ENA FH1_CBC_INT_ENA FH2_CBC_INT_ENA FH0_OST_INT_ENA FH1_OST_INT_ENA FH2_OST_INT_ENA CAP0_INT_ENA CAP1_INT_ENA CAP2_INT_ENA

TIMER0_STOP_INT_ENA :
bits : 0 - 0 (1 bit)

TIMER1_STOP_INT_ENA :
bits : 1 - 1 (1 bit)

TIMER2_STOP_INT_ENA :
bits : 2 - 2 (1 bit)

TIMER0_TEZ_INT_ENA :
bits : 3 - 3 (1 bit)

TIMER1_TEZ_INT_ENA :
bits : 4 - 4 (1 bit)

TIMER2_TEZ_INT_ENA :
bits : 5 - 5 (1 bit)

TIMER0_TEP_INT_ENA :
bits : 6 - 6 (1 bit)

TIMER1_TEP_INT_ENA :
bits : 7 - 7 (1 bit)

TIMER2_TEP_INT_ENA :
bits : 8 - 8 (1 bit)

FAULT0_INT_ENA :
bits : 9 - 9 (1 bit)

FAULT1_INT_ENA :
bits : 10 - 10 (1 bit)

FAULT2_INT_ENA :
bits : 11 - 11 (1 bit)

FAULT0_CLR_INT_ENA :
bits : 12 - 12 (1 bit)

FAULT1_CLR_INT_ENA :
bits : 13 - 13 (1 bit)

FAULT2_CLR_INT_ENA :
bits : 14 - 14 (1 bit)

OP0_TEA_INT_ENA :
bits : 15 - 15 (1 bit)

OP1_TEA_INT_ENA :
bits : 16 - 16 (1 bit)

OP2_TEA_INT_ENA :
bits : 17 - 17 (1 bit)

OP0_TEB_INT_ENA :
bits : 18 - 18 (1 bit)

OP1_TEB_INT_ENA :
bits : 19 - 19 (1 bit)

OP2_TEB_INT_ENA :
bits : 20 - 20 (1 bit)

FH0_CBC_INT_ENA :
bits : 21 - 21 (1 bit)

FH1_CBC_INT_ENA :
bits : 22 - 22 (1 bit)

FH2_CBC_INT_ENA :
bits : 23 - 23 (1 bit)

FH0_OST_INT_ENA :
bits : 24 - 24 (1 bit)

FH1_OST_INT_ENA :
bits : 25 - 25 (1 bit)

FH2_OST_INT_ENA :
bits : 26 - 26 (1 bit)

CAP0_INT_ENA :
bits : 27 - 27 (1 bit)

CAP1_INT_ENA :
bits : 28 - 28 (1 bit)

CAP2_INT_ENA :
bits : 29 - 29 (1 bit)


MCMCPWM_INT_RAW_MCPWM

MCMCPWM_INT_RAW_MCPWM
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMCPWM_INT_RAW_MCPWM MCMCPWM_INT_RAW_MCPWM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_STOP_INT_RAW TIMER1_STOP_INT_RAW TIMER2_STOP_INT_RAW TIMER0_TEZ_INT_RAW TIMER1_TEZ_INT_RAW TIMER2_TEZ_INT_RAW TIMER0_TEP_INT_RAW TIMER1_TEP_INT_RAW TIMER2_TEP_INT_RAW FAULT0_INT_RAW FAULT1_INT_RAW FAULT2_INT_RAW FAULT0_CLR_INT_RAW FAULT1_CLR_INT_RAW FAULT2_CLR_INT_RAW OP0_TEA_INT_RAW OP1_TEA_INT_RAW OP2_TEA_INT_RAW OP0_TEB_INT_RAW OP1_TEB_INT_RAW OP2_TEB_INT_RAW FH0_CBC_INT_RAW FH1_CBC_INT_RAW FH2_CBC_INT_RAW FH0_OST_INT_RAW FH1_OST_INT_RAW FH2_OST_INT_RAW CAP0_INT_RAW CAP1_INT_RAW CAP2_INT_RAW

TIMER0_STOP_INT_RAW :
bits : 0 - 0 (1 bit)

TIMER1_STOP_INT_RAW :
bits : 1 - 1 (1 bit)

TIMER2_STOP_INT_RAW :
bits : 2 - 2 (1 bit)

TIMER0_TEZ_INT_RAW :
bits : 3 - 3 (1 bit)

TIMER1_TEZ_INT_RAW :
bits : 4 - 4 (1 bit)

TIMER2_TEZ_INT_RAW :
bits : 5 - 5 (1 bit)

TIMER0_TEP_INT_RAW :
bits : 6 - 6 (1 bit)

TIMER1_TEP_INT_RAW :
bits : 7 - 7 (1 bit)

TIMER2_TEP_INT_RAW :
bits : 8 - 8 (1 bit)

FAULT0_INT_RAW :
bits : 9 - 9 (1 bit)

FAULT1_INT_RAW :
bits : 10 - 10 (1 bit)

FAULT2_INT_RAW :
bits : 11 - 11 (1 bit)

FAULT0_CLR_INT_RAW :
bits : 12 - 12 (1 bit)

FAULT1_CLR_INT_RAW :
bits : 13 - 13 (1 bit)

FAULT2_CLR_INT_RAW :
bits : 14 - 14 (1 bit)

OP0_TEA_INT_RAW :
bits : 15 - 15 (1 bit)

OP1_TEA_INT_RAW :
bits : 16 - 16 (1 bit)

OP2_TEA_INT_RAW :
bits : 17 - 17 (1 bit)

OP0_TEB_INT_RAW :
bits : 18 - 18 (1 bit)

OP1_TEB_INT_RAW :
bits : 19 - 19 (1 bit)

OP2_TEB_INT_RAW :
bits : 20 - 20 (1 bit)

FH0_CBC_INT_RAW :
bits : 21 - 21 (1 bit)

FH1_CBC_INT_RAW :
bits : 22 - 22 (1 bit)

FH2_CBC_INT_RAW :
bits : 23 - 23 (1 bit)

FH0_OST_INT_RAW :
bits : 24 - 24 (1 bit)

FH1_OST_INT_RAW :
bits : 25 - 25 (1 bit)

FH2_OST_INT_RAW :
bits : 26 - 26 (1 bit)

CAP0_INT_RAW :
bits : 27 - 27 (1 bit)

CAP1_INT_RAW :
bits : 28 - 28 (1 bit)

CAP2_INT_RAW :
bits : 29 - 29 (1 bit)


MCMCPWM_INT_ST_MCPWM

MCMCPWM_INT_ST_MCPWM
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMCPWM_INT_ST_MCPWM MCMCPWM_INT_ST_MCPWM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_STOP_INT_ST TIMER1_STOP_INT_ST TIMER2_STOP_INT_ST TIMER0_TEZ_INT_ST TIMER1_TEZ_INT_ST TIMER2_TEZ_INT_ST TIMER0_TEP_INT_ST TIMER1_TEP_INT_ST TIMER2_TEP_INT_ST FAULT0_INT_ST FAULT1_INT_ST FAULT2_INT_ST FAULT0_CLR_INT_ST FAULT1_CLR_INT_ST FAULT2_CLR_INT_ST OP0_TEA_INT_ST OP1_TEA_INT_ST OP2_TEA_INT_ST OP0_TEB_INT_ST OP1_TEB_INT_ST OP2_TEB_INT_ST FH0_CBC_INT_ST FH1_CBC_INT_ST FH2_CBC_INT_ST FH0_OST_INT_ST FH1_OST_INT_ST FH2_OST_INT_ST CAP0_INT_ST CAP1_INT_ST CAP2_INT_ST

TIMER0_STOP_INT_ST :
bits : 0 - 0 (1 bit)

TIMER1_STOP_INT_ST :
bits : 1 - 1 (1 bit)

TIMER2_STOP_INT_ST :
bits : 2 - 2 (1 bit)

TIMER0_TEZ_INT_ST :
bits : 3 - 3 (1 bit)

TIMER1_TEZ_INT_ST :
bits : 4 - 4 (1 bit)

TIMER2_TEZ_INT_ST :
bits : 5 - 5 (1 bit)

TIMER0_TEP_INT_ST :
bits : 6 - 6 (1 bit)

TIMER1_TEP_INT_ST :
bits : 7 - 7 (1 bit)

TIMER2_TEP_INT_ST :
bits : 8 - 8 (1 bit)

FAULT0_INT_ST :
bits : 9 - 9 (1 bit)

FAULT1_INT_ST :
bits : 10 - 10 (1 bit)

FAULT2_INT_ST :
bits : 11 - 11 (1 bit)

FAULT0_CLR_INT_ST :
bits : 12 - 12 (1 bit)

FAULT1_CLR_INT_ST :
bits : 13 - 13 (1 bit)

FAULT2_CLR_INT_ST :
bits : 14 - 14 (1 bit)

OP0_TEA_INT_ST :
bits : 15 - 15 (1 bit)

OP1_TEA_INT_ST :
bits : 16 - 16 (1 bit)

OP2_TEA_INT_ST :
bits : 17 - 17 (1 bit)

OP0_TEB_INT_ST :
bits : 18 - 18 (1 bit)

OP1_TEB_INT_ST :
bits : 19 - 19 (1 bit)

OP2_TEB_INT_ST :
bits : 20 - 20 (1 bit)

FH0_CBC_INT_ST :
bits : 21 - 21 (1 bit)

FH1_CBC_INT_ST :
bits : 22 - 22 (1 bit)

FH2_CBC_INT_ST :
bits : 23 - 23 (1 bit)

FH0_OST_INT_ST :
bits : 24 - 24 (1 bit)

FH1_OST_INT_ST :
bits : 25 - 25 (1 bit)

FH2_OST_INT_ST :
bits : 26 - 26 (1 bit)

CAP0_INT_ST :
bits : 27 - 27 (1 bit)

CAP1_INT_ST :
bits : 28 - 28 (1 bit)

CAP2_INT_ST :
bits : 29 - 29 (1 bit)


MCMCPWM_INT_CLR_MCPWM

MCMCPWM_INT_CLR_MCPWM
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMCPWM_INT_CLR_MCPWM MCMCPWM_INT_CLR_MCPWM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_STOP_INT_CLR TIMER1_STOP_INT_CLR TIMER2_STOP_INT_CLR TIMER0_TEZ_INT_CLR TIMER1_TEZ_INT_CLR TIMER2_TEZ_INT_CLR TIMER0_TEP_INT_CLR TIMER1_TEP_INT_CLR TIMER2_TEP_INT_CLR FAULT0_INT_CLR FAULT1_INT_CLR FAULT2_INT_CLR FAULT0_CLR_INT_CLR FAULT1_CLR_INT_CLR FAULT2_CLR_INT_CLR OP0_TEA_INT_CLR OP1_TEA_INT_CLR OP2_TEA_INT_CLR OP0_TEB_INT_CLR OP1_TEB_INT_CLR OP2_TEB_INT_CLR FH0_CBC_INT_CLR FH1_CBC_INT_CLR FH2_CBC_INT_CLR FH0_OST_INT_CLR FH1_OST_INT_CLR FH2_OST_INT_CLR CAP0_INT_CLR CAP1_INT_CLR CAP2_INT_CLR

TIMER0_STOP_INT_CLR :
bits : 0 - 0 (1 bit)

TIMER1_STOP_INT_CLR :
bits : 1 - 1 (1 bit)

TIMER2_STOP_INT_CLR :
bits : 2 - 2 (1 bit)

TIMER0_TEZ_INT_CLR :
bits : 3 - 3 (1 bit)

TIMER1_TEZ_INT_CLR :
bits : 4 - 4 (1 bit)

TIMER2_TEZ_INT_CLR :
bits : 5 - 5 (1 bit)

TIMER0_TEP_INT_CLR :
bits : 6 - 6 (1 bit)

TIMER1_TEP_INT_CLR :
bits : 7 - 7 (1 bit)

TIMER2_TEP_INT_CLR :
bits : 8 - 8 (1 bit)

FAULT0_INT_CLR :
bits : 9 - 9 (1 bit)

FAULT1_INT_CLR :
bits : 10 - 10 (1 bit)

FAULT2_INT_CLR :
bits : 11 - 11 (1 bit)

FAULT0_CLR_INT_CLR :
bits : 12 - 12 (1 bit)

FAULT1_CLR_INT_CLR :
bits : 13 - 13 (1 bit)

FAULT2_CLR_INT_CLR :
bits : 14 - 14 (1 bit)

OP0_TEA_INT_CLR :
bits : 15 - 15 (1 bit)

OP1_TEA_INT_CLR :
bits : 16 - 16 (1 bit)

OP2_TEA_INT_CLR :
bits : 17 - 17 (1 bit)

OP0_TEB_INT_CLR :
bits : 18 - 18 (1 bit)

OP1_TEB_INT_CLR :
bits : 19 - 19 (1 bit)

OP2_TEB_INT_CLR :
bits : 20 - 20 (1 bit)

FH0_CBC_INT_CLR :
bits : 21 - 21 (1 bit)

FH1_CBC_INT_CLR :
bits : 22 - 22 (1 bit)

FH2_CBC_INT_CLR :
bits : 23 - 23 (1 bit)

FH0_OST_INT_CLR :
bits : 24 - 24 (1 bit)

FH1_OST_INT_CLR :
bits : 25 - 25 (1 bit)

FH2_OST_INT_CLR :
bits : 26 - 26 (1 bit)

CAP0_INT_CLR :
bits : 27 - 27 (1 bit)

CAP1_INT_CLR :
bits : 28 - 28 (1 bit)

CAP2_INT_CLR :
bits : 29 - 29 (1 bit)


CLK

MCPWM_CLK
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_EN

CLK_EN :
bits : 0 - 0 (1 bit)


VERSION

MCPWM_VERSION
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 27 (28 bit)


TIMER1_CFG0

MCPWM_TIMER1_CFG0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CFG0 TIMER1_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_PRESCALE TIMER1_PERIOD TIMER1_PERIOD_UPMETHOD

TIMER1_PRESCALE :
bits : 0 - 7 (8 bit)

TIMER1_PERIOD :
bits : 8 - 23 (16 bit)

TIMER1_PERIOD_UPMETHOD :
bits : 24 - 25 (2 bit)


TIMER1_CFG1

MCPWM_TIMER1_CFG1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CFG1 TIMER1_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_START TIMER1_MOD

TIMER1_START :
bits : 0 - 2 (3 bit)

TIMER1_MOD :
bits : 3 - 4 (2 bit)


TIMER1_SYNC

MCPWM_TIMER1_SYNC
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_SYNC TIMER1_SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_SYNCI_EN TIMER1_SYNC_SW TIMER1_SYNCO_SEL TIMER1_PHASE

TIMER1_SYNCI_EN :
bits : 0 - 0 (1 bit)

TIMER1_SYNC_SW :
bits : 1 - 1 (1 bit)

TIMER1_SYNCO_SEL :
bits : 2 - 3 (2 bit)

TIMER1_PHASE :
bits : 4 - 20 (17 bit)


TIMER1_STATUS

MCPWM_TIMER1_STATUS
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_STATUS TIMER1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_VALUE TIMER1_DIRECTION

TIMER1_VALUE :
bits : 0 - 15 (16 bit)

TIMER1_DIRECTION :
bits : 16 - 16 (1 bit)


TIMER2_CFG0

MCPWM_TIMER2_CFG0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CFG0 TIMER2_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER2_PRESCALE TIMER2_PERIOD TIMER2_PERIOD_UPMETHOD

TIMER2_PRESCALE :
bits : 0 - 7 (8 bit)

TIMER2_PERIOD :
bits : 8 - 23 (16 bit)

TIMER2_PERIOD_UPMETHOD :
bits : 24 - 25 (2 bit)


TIMER2_CFG1

MCPWM_TIMER2_CFG1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CFG1 TIMER2_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER2_START TIMER2_MOD

TIMER2_START :
bits : 0 - 2 (3 bit)

TIMER2_MOD :
bits : 3 - 4 (2 bit)


TIMER2_SYNC

MCPWM_TIMER2_SYNC
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_SYNC TIMER2_SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER2_SYNCI_EN TIMER2_SYNC_SW TIMER2_SYNCO_SEL TIMER2_PHASE

TIMER2_SYNCI_EN :
bits : 0 - 0 (1 bit)

TIMER2_SYNC_SW :
bits : 1 - 1 (1 bit)

TIMER2_SYNCO_SEL :
bits : 2 - 3 (2 bit)

TIMER2_PHASE :
bits : 4 - 20 (17 bit)


TIMER2_STATUS

MCPWM_TIMER2_STATUS
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_STATUS TIMER2_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER2_VALUE TIMER2_DIRECTION

TIMER2_VALUE :
bits : 0 - 15 (16 bit)

TIMER2_DIRECTION :
bits : 16 - 16 (1 bit)


TIMER_SYNCI_CFG

MCPWM_TIMER_SYNCI_CFG
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_SYNCI_CFG TIMER_SYNCI_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_SYNCISEL TIMER1_SYNCISEL TIMER2_SYNCISEL EXTERNAL_SYNCI0_INVERT EXTERNAL_SYNCI1_INVERT EXTERNAL_SYNCI2_INVERT

TIMER0_SYNCISEL :
bits : 0 - 2 (3 bit)

TIMER1_SYNCISEL :
bits : 3 - 5 (3 bit)

TIMER2_SYNCISEL :
bits : 6 - 8 (3 bit)

EXTERNAL_SYNCI0_INVERT :
bits : 9 - 9 (1 bit)

EXTERNAL_SYNCI1_INVERT :
bits : 10 - 10 (1 bit)

EXTERNAL_SYNCI2_INVERT :
bits : 11 - 11 (1 bit)


OPERATOR_TIMERSEL

MCPWM_OPERATOR_TIMERSEL
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPERATOR_TIMERSEL OPERATOR_TIMERSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPERATOR0_TIMERSEL OPERATOR1_TIMERSEL OPERATOR2_TIMERSEL

OPERATOR0_TIMERSEL :
bits : 0 - 1 (2 bit)

OPERATOR1_TIMERSEL :
bits : 2 - 3 (2 bit)

OPERATOR2_TIMERSEL :
bits : 4 - 5 (2 bit)


GEN0_STMP_CFG

MCPWM_GEN0_STMP_CFG
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_STMP_CFG GEN0_STMP_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_A_UPMETHOD GEN0_B_UPMETHOD GEN0_A_SHDW_FULL GEN0_B_SHDW_FULL

GEN0_A_UPMETHOD :
bits : 0 - 3 (4 bit)

GEN0_B_UPMETHOD :
bits : 4 - 7 (4 bit)

GEN0_A_SHDW_FULL :
bits : 8 - 8 (1 bit)

GEN0_B_SHDW_FULL :
bits : 9 - 9 (1 bit)


TIMER0_CFG0

MCPWM_TIMER0_CFG0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CFG0 TIMER0_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_PRESCALE TIMER0_PERIOD TIMER0_PERIOD_UPMETHOD

TIMER0_PRESCALE :
bits : 0 - 7 (8 bit)

TIMER0_PERIOD :
bits : 8 - 23 (16 bit)

TIMER0_PERIOD_UPMETHOD :
bits : 24 - 25 (2 bit)


GEN0_TSTMP_A

MCPWM_GEN0_TSTMP_A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_TSTMP_A GEN0_TSTMP_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_A

GEN0_A :
bits : 0 - 15 (16 bit)


GEN0_TSTMP_B

MCPWM_GEN0_TSTMP_B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_TSTMP_B GEN0_TSTMP_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_B

GEN0_B :
bits : 0 - 15 (16 bit)


GEN0_CFG0

MCPWM_GEN0_CFG0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_CFG0 GEN0_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_CFG_UPMETHOD GEN0_T0_SEL GEN0_T1_SEL

GEN0_CFG_UPMETHOD :
bits : 0 - 3 (4 bit)

GEN0_T0_SEL :
bits : 4 - 6 (3 bit)

GEN0_T1_SEL :
bits : 7 - 9 (3 bit)


GEN0_FORCE

MCPWM_GEN0_FORCE
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_FORCE GEN0_FORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_CNTUFORCE_UPMETHOD GEN0_A_CNTUFORCE_MODE GEN0_B_CNTUFORCE_MODE GEN0_A_NCIFORCE GEN0_A_NCIFORCE_MODE GEN0_B_NCIFORCE GEN0_B_NCIFORCE_MODE

GEN0_CNTUFORCE_UPMETHOD :
bits : 0 - 5 (6 bit)

GEN0_A_CNTUFORCE_MODE :
bits : 6 - 7 (2 bit)

GEN0_B_CNTUFORCE_MODE :
bits : 8 - 9 (2 bit)

GEN0_A_NCIFORCE :
bits : 10 - 10 (1 bit)

GEN0_A_NCIFORCE_MODE :
bits : 11 - 12 (2 bit)

GEN0_B_NCIFORCE :
bits : 13 - 13 (1 bit)

GEN0_B_NCIFORCE_MODE :
bits : 14 - 15 (2 bit)


GEN0_A

MCPWM_GEN0_A
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_A GEN0_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_A_UTEZ GEN0_A_UTEP GEN0_A_UTEA GEN0_A_UTEB GEN0_A_UT0 GEN0_A_UT1 GEN0_A_DTEZ GEN0_A_DTEP GEN0_A_DTEA GEN0_A_DTEB GEN0_A_DT0 GEN0_A_DT1

GEN0_A_UTEZ :
bits : 0 - 1 (2 bit)

GEN0_A_UTEP :
bits : 2 - 3 (2 bit)

GEN0_A_UTEA :
bits : 4 - 5 (2 bit)

GEN0_A_UTEB :
bits : 6 - 7 (2 bit)

GEN0_A_UT0 :
bits : 8 - 9 (2 bit)

GEN0_A_UT1 :
bits : 10 - 11 (2 bit)

GEN0_A_DTEZ :
bits : 12 - 13 (2 bit)

GEN0_A_DTEP :
bits : 14 - 15 (2 bit)

GEN0_A_DTEA :
bits : 16 - 17 (2 bit)

GEN0_A_DTEB :
bits : 18 - 19 (2 bit)

GEN0_A_DT0 :
bits : 20 - 21 (2 bit)

GEN0_A_DT1 :
bits : 22 - 23 (2 bit)


GEN0_B

MCPWM_GEN0_B
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN0_B GEN0_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN0_B_UTEZ GEN0_B_UTEP GEN0_B_UTEA GEN0_B_UTEB GEN0_B_UT0 GEN0_B_UT1 GEN0_B_DTEZ GEN0_B_DTEP GEN0_B_DTEA GEN0_B_DTEB GEN0_B_DT0 GEN0_B_DT1

GEN0_B_UTEZ :
bits : 0 - 1 (2 bit)

GEN0_B_UTEP :
bits : 2 - 3 (2 bit)

GEN0_B_UTEA :
bits : 4 - 5 (2 bit)

GEN0_B_UTEB :
bits : 6 - 7 (2 bit)

GEN0_B_UT0 :
bits : 8 - 9 (2 bit)

GEN0_B_UT1 :
bits : 10 - 11 (2 bit)

GEN0_B_DTEZ :
bits : 12 - 13 (2 bit)

GEN0_B_DTEP :
bits : 14 - 15 (2 bit)

GEN0_B_DTEA :
bits : 16 - 17 (2 bit)

GEN0_B_DTEB :
bits : 18 - 19 (2 bit)

GEN0_B_DT0 :
bits : 20 - 21 (2 bit)

GEN0_B_DT1 :
bits : 22 - 23 (2 bit)


DT0_CFG

MCPWM_DT0_CFG
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT0_CFG DT0_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT0_FED_UPMETHOD DT0_RED_UPMETHOD DT0_DEB_MODE DT0_A_OUTSWAP DT0_B_OUTSWAP DT0_RED_INSEL DT0_FED_INSEL DT0_RED_OUTINVERT DT0_FED_OUTINVERT DT0_A_OUTBYPASS DT0_B_OUTBYPASS DT0_CLK_SEL

DT0_FED_UPMETHOD :
bits : 0 - 3 (4 bit)

DT0_RED_UPMETHOD :
bits : 4 - 7 (4 bit)

DT0_DEB_MODE :
bits : 8 - 8 (1 bit)

DT0_A_OUTSWAP :
bits : 9 - 9 (1 bit)

DT0_B_OUTSWAP :
bits : 10 - 10 (1 bit)

DT0_RED_INSEL :
bits : 11 - 11 (1 bit)

DT0_FED_INSEL :
bits : 12 - 12 (1 bit)

DT0_RED_OUTINVERT :
bits : 13 - 13 (1 bit)

DT0_FED_OUTINVERT :
bits : 14 - 14 (1 bit)

DT0_A_OUTBYPASS :
bits : 15 - 15 (1 bit)

DT0_B_OUTBYPASS :
bits : 16 - 16 (1 bit)

DT0_CLK_SEL :
bits : 17 - 17 (1 bit)


DT0_FED_CFG

MCPWM_DT0_FED_CFG
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT0_FED_CFG DT0_FED_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT0_FED

DT0_FED :
bits : 0 - 15 (16 bit)


DT0_RED_CFG

MCPWM_DT0_RED_CFG
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT0_RED_CFG DT0_RED_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT0_RED

DT0_RED :
bits : 0 - 15 (16 bit)


CARRIER0_CFG

MCPWM_CARRIER0_CFG
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CARRIER0_CFG CARRIER0_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER0_EN CARRIER0_PRESCALE CARRIER0_DUTY CARRIER0_OSHWTH CARRIER0_OUT_INVERT CARRIER0_IN_INVERT

CARRIER0_EN :
bits : 0 - 0 (1 bit)

CARRIER0_PRESCALE :
bits : 1 - 4 (4 bit)

CARRIER0_DUTY :
bits : 5 - 7 (3 bit)

CARRIER0_OSHWTH :
bits : 8 - 11 (4 bit)

CARRIER0_OUT_INVERT :
bits : 12 - 12 (1 bit)

CARRIER0_IN_INVERT :
bits : 13 - 13 (1 bit)


FH0_CFG0

MCPWM_FH0_CFG0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH0_CFG0 FH0_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH0_SW_CBC FH0_F2_CBC FH0_F1_CBC FH0_F0_CBC FH0_SW_OST FH0_F2_OST FH0_F1_OST FH0_F0_OST FH0_A_CBC_D FH0_A_CBC_U FH0_A_OST_D FH0_A_OST_U FH0_B_CBC_D FH0_B_CBC_U FH0_B_OST_D FH0_B_OST_U

FH0_SW_CBC :
bits : 0 - 0 (1 bit)

FH0_F2_CBC :
bits : 1 - 1 (1 bit)

FH0_F1_CBC :
bits : 2 - 2 (1 bit)

FH0_F0_CBC :
bits : 3 - 3 (1 bit)

FH0_SW_OST :
bits : 4 - 4 (1 bit)

FH0_F2_OST :
bits : 5 - 5 (1 bit)

FH0_F1_OST :
bits : 6 - 6 (1 bit)

FH0_F0_OST :
bits : 7 - 7 (1 bit)

FH0_A_CBC_D :
bits : 8 - 9 (2 bit)

FH0_A_CBC_U :
bits : 10 - 11 (2 bit)

FH0_A_OST_D :
bits : 12 - 13 (2 bit)

FH0_A_OST_U :
bits : 14 - 15 (2 bit)

FH0_B_CBC_D :
bits : 16 - 17 (2 bit)

FH0_B_CBC_U :
bits : 18 - 19 (2 bit)

FH0_B_OST_D :
bits : 20 - 21 (2 bit)

FH0_B_OST_U :
bits : 22 - 23 (2 bit)


FH0_CFG1

MCPWM_FH0_CFG1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH0_CFG1 FH0_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH0_CLR_OST FH0_CBCPULSE FH0_FORCE_CBC FH0_FORCE_OST

FH0_CLR_OST :
bits : 0 - 0 (1 bit)

FH0_CBCPULSE :
bits : 1 - 2 (2 bit)

FH0_FORCE_CBC :
bits : 3 - 3 (1 bit)

FH0_FORCE_OST :
bits : 4 - 4 (1 bit)


FH0_STATUS

MCPWM_FH0_STATUS
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH0_STATUS FH0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH0_CBC_ON FH0_OST_ON

FH0_CBC_ON :
bits : 0 - 0 (1 bit)

FH0_OST_ON :
bits : 1 - 1 (1 bit)


GEN1_STMP_CFG

MCPWM_GEN1_STMP_CFG
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_STMP_CFG GEN1_STMP_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_A_UPMETHOD GEN1_B_UPMETHOD GEN1_A_SHDW_FULL GEN1_B_SHDW_FULL

GEN1_A_UPMETHOD :
bits : 0 - 3 (4 bit)

GEN1_B_UPMETHOD :
bits : 4 - 7 (4 bit)

GEN1_A_SHDW_FULL :
bits : 8 - 8 (1 bit)

GEN1_B_SHDW_FULL :
bits : 9 - 9 (1 bit)


GEN1_TSTMP_A

MCPWM_GEN1_TSTMP_A
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_TSTMP_A GEN1_TSTMP_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_A

GEN1_A :
bits : 0 - 15 (16 bit)


GEN1_TSTMP_B

MCPWM_GEN1_TSTMP_B
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_TSTMP_B GEN1_TSTMP_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_B

GEN1_B :
bits : 0 - 15 (16 bit)


TIMER0_CFG1

MCPWM_TIMER0_CFG1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CFG1 TIMER0_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_START TIMER0_MOD

TIMER0_START :
bits : 0 - 2 (3 bit)

TIMER0_MOD :
bits : 3 - 4 (2 bit)


GEN1_CFG0

MCPWM_GEN1_CFG0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_CFG0 GEN1_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_CFG_UPMETHOD GEN1_T0_SEL GEN1_T1_SEL

GEN1_CFG_UPMETHOD :
bits : 0 - 3 (4 bit)

GEN1_T0_SEL :
bits : 4 - 6 (3 bit)

GEN1_T1_SEL :
bits : 7 - 9 (3 bit)


GEN1_FORCE

MCPWM_GEN1_FORCE
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_FORCE GEN1_FORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_CNTUFORCE_UPMETHOD GEN1_A_CNTUFORCE_MODE GEN1_B_CNTUFORCE_MODE GEN1_A_NCIFORCE GEN1_A_NCIFORCE_MODE GEN1_B_NCIFORCE GEN1_B_NCIFORCE_MODE

GEN1_CNTUFORCE_UPMETHOD :
bits : 0 - 5 (6 bit)

GEN1_A_CNTUFORCE_MODE :
bits : 6 - 7 (2 bit)

GEN1_B_CNTUFORCE_MODE :
bits : 8 - 9 (2 bit)

GEN1_A_NCIFORCE :
bits : 10 - 10 (1 bit)

GEN1_A_NCIFORCE_MODE :
bits : 11 - 12 (2 bit)

GEN1_B_NCIFORCE :
bits : 13 - 13 (1 bit)

GEN1_B_NCIFORCE_MODE :
bits : 14 - 15 (2 bit)


GEN1_A

MCPWM_GEN1_A
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_A GEN1_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_A_UTEZ GEN1_A_UTEP GEN1_A_UTEA GEN1_A_UTEB GEN1_A_UT0 GEN1_A_UT1 GEN1_A_DTEZ GEN1_A_DTEP GEN1_A_DTEA GEN1_A_DTEB GEN1_A_DT0 GEN1_A_DT1

GEN1_A_UTEZ :
bits : 0 - 1 (2 bit)

GEN1_A_UTEP :
bits : 2 - 3 (2 bit)

GEN1_A_UTEA :
bits : 4 - 5 (2 bit)

GEN1_A_UTEB :
bits : 6 - 7 (2 bit)

GEN1_A_UT0 :
bits : 8 - 9 (2 bit)

GEN1_A_UT1 :
bits : 10 - 11 (2 bit)

GEN1_A_DTEZ :
bits : 12 - 13 (2 bit)

GEN1_A_DTEP :
bits : 14 - 15 (2 bit)

GEN1_A_DTEA :
bits : 16 - 17 (2 bit)

GEN1_A_DTEB :
bits : 18 - 19 (2 bit)

GEN1_A_DT0 :
bits : 20 - 21 (2 bit)

GEN1_A_DT1 :
bits : 22 - 23 (2 bit)


GEN1_B

MCPWM_GEN1_B
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN1_B GEN1_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN1_B_UTEZ GEN1_B_UTEP GEN1_B_UTEA GEN1_B_UTEB GEN1_B_UT0 GEN1_B_UT1 GEN1_B_DTEZ GEN1_B_DTEP GEN1_B_DTEA GEN1_B_DTEB GEN1_B_DT0 GEN1_B_DT1

GEN1_B_UTEZ :
bits : 0 - 1 (2 bit)

GEN1_B_UTEP :
bits : 2 - 3 (2 bit)

GEN1_B_UTEA :
bits : 4 - 5 (2 bit)

GEN1_B_UTEB :
bits : 6 - 7 (2 bit)

GEN1_B_UT0 :
bits : 8 - 9 (2 bit)

GEN1_B_UT1 :
bits : 10 - 11 (2 bit)

GEN1_B_DTEZ :
bits : 12 - 13 (2 bit)

GEN1_B_DTEP :
bits : 14 - 15 (2 bit)

GEN1_B_DTEA :
bits : 16 - 17 (2 bit)

GEN1_B_DTEB :
bits : 18 - 19 (2 bit)

GEN1_B_DT0 :
bits : 20 - 21 (2 bit)

GEN1_B_DT1 :
bits : 22 - 23 (2 bit)


DT1_CFG

MCPWM_DT1_CFG
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT1_CFG DT1_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT1_FED_UPMETHOD DT1_RED_UPMETHOD DT1_DEB_MODE DT1_A_OUTSWAP DT1_B_OUTSWAP DT1_RED_INSEL DT1_FED_INSEL DT1_RED_OUTINVERT DT1_FED_OUTINVERT DT1_A_OUTBYPASS DT1_B_OUTBYPASS DT1_CLK_SEL

DT1_FED_UPMETHOD :
bits : 0 - 3 (4 bit)

DT1_RED_UPMETHOD :
bits : 4 - 7 (4 bit)

DT1_DEB_MODE :
bits : 8 - 8 (1 bit)

DT1_A_OUTSWAP :
bits : 9 - 9 (1 bit)

DT1_B_OUTSWAP :
bits : 10 - 10 (1 bit)

DT1_RED_INSEL :
bits : 11 - 11 (1 bit)

DT1_FED_INSEL :
bits : 12 - 12 (1 bit)

DT1_RED_OUTINVERT :
bits : 13 - 13 (1 bit)

DT1_FED_OUTINVERT :
bits : 14 - 14 (1 bit)

DT1_A_OUTBYPASS :
bits : 15 - 15 (1 bit)

DT1_B_OUTBYPASS :
bits : 16 - 16 (1 bit)

DT1_CLK_SEL :
bits : 17 - 17 (1 bit)


DT1_FED_CFG

MCPWM_DT1_FED_CFG
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT1_FED_CFG DT1_FED_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT1_FED

DT1_FED :
bits : 0 - 15 (16 bit)


DT1_RED_CFG

MCPWM_DT1_RED_CFG
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT1_RED_CFG DT1_RED_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT1_RED

DT1_RED :
bits : 0 - 15 (16 bit)


CARRIER1_CFG

MCPWM_CARRIER1_CFG
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CARRIER1_CFG CARRIER1_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER1_EN CARRIER1_PRESCALE CARRIER1_DUTY CARRIER1_OSHWTH CARRIER1_OUT_INVERT CARRIER1_IN_INVERT

CARRIER1_EN :
bits : 0 - 0 (1 bit)

CARRIER1_PRESCALE :
bits : 1 - 4 (4 bit)

CARRIER1_DUTY :
bits : 5 - 7 (3 bit)

CARRIER1_OSHWTH :
bits : 8 - 11 (4 bit)

CARRIER1_OUT_INVERT :
bits : 12 - 12 (1 bit)

CARRIER1_IN_INVERT :
bits : 13 - 13 (1 bit)


FH1_CFG0

MCPWM_FH1_CFG0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH1_CFG0 FH1_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH1_SW_CBC FH1_F2_CBC FH1_F1_CBC FH1_F0_CBC FH1_SW_OST FH1_F2_OST FH1_F1_OST FH1_F0_OST FH1_A_CBC_D FH1_A_CBC_U FH1_A_OST_D FH1_A_OST_U FH1_B_CBC_D FH1_B_CBC_U FH1_B_OST_D FH1_B_OST_U

FH1_SW_CBC :
bits : 0 - 0 (1 bit)

FH1_F2_CBC :
bits : 1 - 1 (1 bit)

FH1_F1_CBC :
bits : 2 - 2 (1 bit)

FH1_F0_CBC :
bits : 3 - 3 (1 bit)

FH1_SW_OST :
bits : 4 - 4 (1 bit)

FH1_F2_OST :
bits : 5 - 5 (1 bit)

FH1_F1_OST :
bits : 6 - 6 (1 bit)

FH1_F0_OST :
bits : 7 - 7 (1 bit)

FH1_A_CBC_D :
bits : 8 - 9 (2 bit)

FH1_A_CBC_U :
bits : 10 - 11 (2 bit)

FH1_A_OST_D :
bits : 12 - 13 (2 bit)

FH1_A_OST_U :
bits : 14 - 15 (2 bit)

FH1_B_CBC_D :
bits : 16 - 17 (2 bit)

FH1_B_CBC_U :
bits : 18 - 19 (2 bit)

FH1_B_OST_D :
bits : 20 - 21 (2 bit)

FH1_B_OST_U :
bits : 22 - 23 (2 bit)


FH1_CFG1

MCPWM_FH1_CFG1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH1_CFG1 FH1_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH1_CLR_OST FH1_CBCPULSE FH1_FORCE_CBC FH1_FORCE_OST

FH1_CLR_OST :
bits : 0 - 0 (1 bit)

FH1_CBCPULSE :
bits : 1 - 2 (2 bit)

FH1_FORCE_CBC :
bits : 3 - 3 (1 bit)

FH1_FORCE_OST :
bits : 4 - 4 (1 bit)


FH1_STATUS

MCPWM_FH1_STATUS
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH1_STATUS FH1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH1_CBC_ON FH1_OST_ON

FH1_CBC_ON :
bits : 0 - 0 (1 bit)

FH1_OST_ON :
bits : 1 - 1 (1 bit)


GEN2_STMP_CFG

MCPWM_GEN2_STMP_CFG
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_STMP_CFG GEN2_STMP_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_A_UPMETHOD GEN2_B_UPMETHOD GEN2_A_SHDW_FULL GEN2_B_SHDW_FULL

GEN2_A_UPMETHOD :
bits : 0 - 3 (4 bit)

GEN2_B_UPMETHOD :
bits : 4 - 7 (4 bit)

GEN2_A_SHDW_FULL :
bits : 8 - 8 (1 bit)

GEN2_B_SHDW_FULL :
bits : 9 - 9 (1 bit)


GEN2_TSTMP_A

MCPWM_GEN2_TSTMP_A
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_TSTMP_A GEN2_TSTMP_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_A

GEN2_A :
bits : 0 - 15 (16 bit)


GEN2_TSTMP_B

MCPWM_GEN2_TSTMP_B
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_TSTMP_B GEN2_TSTMP_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_B

GEN2_B :
bits : 0 - 15 (16 bit)


GEN2_CFG0

MCPWM_GEN2_CFG0
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_CFG0 GEN2_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_CFG_UPMETHOD GEN2_T0_SEL GEN2_T1_SEL

GEN2_CFG_UPMETHOD :
bits : 0 - 3 (4 bit)

GEN2_T0_SEL :
bits : 4 - 6 (3 bit)

GEN2_T1_SEL :
bits : 7 - 9 (3 bit)


GEN2_FORCE

MCPWM_GEN2_FORCE
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_FORCE GEN2_FORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_CNTUFORCE_UPMETHOD GEN2_A_CNTUFORCE_MODE GEN2_B_CNTUFORCE_MODE GEN2_A_NCIFORCE GEN2_A_NCIFORCE_MODE GEN2_B_NCIFORCE GEN2_B_NCIFORCE_MODE

GEN2_CNTUFORCE_UPMETHOD :
bits : 0 - 5 (6 bit)

GEN2_A_CNTUFORCE_MODE :
bits : 6 - 7 (2 bit)

GEN2_B_CNTUFORCE_MODE :
bits : 8 - 9 (2 bit)

GEN2_A_NCIFORCE :
bits : 10 - 10 (1 bit)

GEN2_A_NCIFORCE_MODE :
bits : 11 - 12 (2 bit)

GEN2_B_NCIFORCE :
bits : 13 - 13 (1 bit)

GEN2_B_NCIFORCE_MODE :
bits : 14 - 15 (2 bit)


TIMER0_SYNC

MCPWM_TIMER0_SYNC
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_SYNC TIMER0_SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_SYNCI_EN TIMER0_SYNC_SW TIMER0_SYNCO_SEL TIMER0_PHASE

TIMER0_SYNCI_EN :
bits : 0 - 0 (1 bit)

TIMER0_SYNC_SW :
bits : 1 - 1 (1 bit)

TIMER0_SYNCO_SEL :
bits : 2 - 3 (2 bit)

TIMER0_PHASE :
bits : 4 - 20 (17 bit)


GEN2_A

MCPWM_GEN2_A
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_A GEN2_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_A_UTEZ GEN2_A_UTEP GEN2_A_UTEA GEN2_A_UTEB GEN2_A_UT0 GEN2_A_UT1 GEN2_A_DTEZ GEN2_A_DTEP GEN2_A_DTEA GEN2_A_DTEB GEN2_A_DT0 GEN2_A_DT1

GEN2_A_UTEZ :
bits : 0 - 1 (2 bit)

GEN2_A_UTEP :
bits : 2 - 3 (2 bit)

GEN2_A_UTEA :
bits : 4 - 5 (2 bit)

GEN2_A_UTEB :
bits : 6 - 7 (2 bit)

GEN2_A_UT0 :
bits : 8 - 9 (2 bit)

GEN2_A_UT1 :
bits : 10 - 11 (2 bit)

GEN2_A_DTEZ :
bits : 12 - 13 (2 bit)

GEN2_A_DTEP :
bits : 14 - 15 (2 bit)

GEN2_A_DTEA :
bits : 16 - 17 (2 bit)

GEN2_A_DTEB :
bits : 18 - 19 (2 bit)

GEN2_A_DT0 :
bits : 20 - 21 (2 bit)

GEN2_A_DT1 :
bits : 22 - 23 (2 bit)


GEN2_B

MCPWM_GEN2_B
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN2_B GEN2_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN2_B_UTEZ GEN2_B_UTEP GEN2_B_UTEA GEN2_B_UTEB GEN2_B_UT0 GEN2_B_UT1 GEN2_B_DTEZ GEN2_B_DTEP GEN2_B_DTEA GEN2_B_DTEB GEN2_B_DT0 GEN2_B_DT1

GEN2_B_UTEZ :
bits : 0 - 1 (2 bit)

GEN2_B_UTEP :
bits : 2 - 3 (2 bit)

GEN2_B_UTEA :
bits : 4 - 5 (2 bit)

GEN2_B_UTEB :
bits : 6 - 7 (2 bit)

GEN2_B_UT0 :
bits : 8 - 9 (2 bit)

GEN2_B_UT1 :
bits : 10 - 11 (2 bit)

GEN2_B_DTEZ :
bits : 12 - 13 (2 bit)

GEN2_B_DTEP :
bits : 14 - 15 (2 bit)

GEN2_B_DTEA :
bits : 16 - 17 (2 bit)

GEN2_B_DTEB :
bits : 18 - 19 (2 bit)

GEN2_B_DT0 :
bits : 20 - 21 (2 bit)

GEN2_B_DT1 :
bits : 22 - 23 (2 bit)


DT2_CFG

MCPWM_DT2_CFG
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT2_CFG DT2_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT2_FED_UPMETHOD DT2_RED_UPMETHOD DT2_DEB_MODE DT2_A_OUTSWAP DT2_B_OUTSWAP DT2_RED_INSEL DT2_FED_INSEL DT2_RED_OUTINVERT DT2_FED_OUTINVERT DT2_A_OUTBYPASS DT2_B_OUTBYPASS DT2_CLK_SEL

DT2_FED_UPMETHOD :
bits : 0 - 3 (4 bit)

DT2_RED_UPMETHOD :
bits : 4 - 7 (4 bit)

DT2_DEB_MODE :
bits : 8 - 8 (1 bit)

DT2_A_OUTSWAP :
bits : 9 - 9 (1 bit)

DT2_B_OUTSWAP :
bits : 10 - 10 (1 bit)

DT2_RED_INSEL :
bits : 11 - 11 (1 bit)

DT2_FED_INSEL :
bits : 12 - 12 (1 bit)

DT2_RED_OUTINVERT :
bits : 13 - 13 (1 bit)

DT2_FED_OUTINVERT :
bits : 14 - 14 (1 bit)

DT2_A_OUTBYPASS :
bits : 15 - 15 (1 bit)

DT2_B_OUTBYPASS :
bits : 16 - 16 (1 bit)

DT2_CLK_SEL :
bits : 17 - 17 (1 bit)


DT2_FED_CFG

MCPWM_DT2_FED_CFG
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT2_FED_CFG DT2_FED_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT2_FED

DT2_FED :
bits : 0 - 15 (16 bit)


DT2_RED_CFG

MCPWM_DT2_RED_CFG
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT2_RED_CFG DT2_RED_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT2_RED

DT2_RED :
bits : 0 - 15 (16 bit)


CARRIER2_CFG

MCPWM_CARRIER2_CFG
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CARRIER2_CFG CARRIER2_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARRIER2_EN CARRIER2_PRESCALE CARRIER2_DUTY CARRIER2_OSHWTH CARRIER2_OUT_INVERT CARRIER2_IN_INVERT

CARRIER2_EN :
bits : 0 - 0 (1 bit)

CARRIER2_PRESCALE :
bits : 1 - 4 (4 bit)

CARRIER2_DUTY :
bits : 5 - 7 (3 bit)

CARRIER2_OSHWTH :
bits : 8 - 11 (4 bit)

CARRIER2_OUT_INVERT :
bits : 12 - 12 (1 bit)

CARRIER2_IN_INVERT :
bits : 13 - 13 (1 bit)


FH2_CFG0

MCPWM_FH2_CFG0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH2_CFG0 FH2_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH2_SW_CBC FH2_F2_CBC FH2_F1_CBC FH2_F0_CBC FH2_SW_OST FH2_F2_OST FH2_F1_OST FH2_F0_OST FH2_A_CBC_D FH2_A_CBC_U FH2_A_OST_D FH2_A_OST_U FH2_B_CBC_D FH2_B_CBC_U FH2_B_OST_D FH2_B_OST_U

FH2_SW_CBC :
bits : 0 - 0 (1 bit)

FH2_F2_CBC :
bits : 1 - 1 (1 bit)

FH2_F1_CBC :
bits : 2 - 2 (1 bit)

FH2_F0_CBC :
bits : 3 - 3 (1 bit)

FH2_SW_OST :
bits : 4 - 4 (1 bit)

FH2_F2_OST :
bits : 5 - 5 (1 bit)

FH2_F1_OST :
bits : 6 - 6 (1 bit)

FH2_F0_OST :
bits : 7 - 7 (1 bit)

FH2_A_CBC_D :
bits : 8 - 9 (2 bit)

FH2_A_CBC_U :
bits : 10 - 11 (2 bit)

FH2_A_OST_D :
bits : 12 - 13 (2 bit)

FH2_A_OST_U :
bits : 14 - 15 (2 bit)

FH2_B_CBC_D :
bits : 16 - 17 (2 bit)

FH2_B_CBC_U :
bits : 18 - 19 (2 bit)

FH2_B_OST_D :
bits : 20 - 21 (2 bit)

FH2_B_OST_U :
bits : 22 - 23 (2 bit)


FH2_CFG1

MCPWM_FH2_CFG1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH2_CFG1 FH2_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH2_CLR_OST FH2_CBCPULSE FH2_FORCE_CBC FH2_FORCE_OST

FH2_CLR_OST :
bits : 0 - 0 (1 bit)

FH2_CBCPULSE :
bits : 1 - 2 (2 bit)

FH2_FORCE_CBC :
bits : 3 - 3 (1 bit)

FH2_FORCE_OST :
bits : 4 - 4 (1 bit)


FH2_STATUS

MCPWM_FH2_STATUS
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FH2_STATUS FH2_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FH2_CBC_ON FH2_OST_ON

FH2_CBC_ON :
bits : 0 - 0 (1 bit)

FH2_OST_ON :
bits : 1 - 1 (1 bit)


FAULT_DETECT

MCPWM_FAULT_DETECT
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAULT_DETECT FAULT_DETECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0_EN F1_EN F2_EN F0_POLE F1_POLE F2_POLE EVENT_F0 EVENT_F1 EVENT_F2

F0_EN :
bits : 0 - 0 (1 bit)

F1_EN :
bits : 1 - 1 (1 bit)

F2_EN :
bits : 2 - 2 (1 bit)

F0_POLE :
bits : 3 - 3 (1 bit)

F1_POLE :
bits : 4 - 4 (1 bit)

F2_POLE :
bits : 5 - 5 (1 bit)

EVENT_F0 :
bits : 6 - 6 (1 bit)

EVENT_F1 :
bits : 7 - 7 (1 bit)

EVENT_F2 :
bits : 8 - 8 (1 bit)


CAP_TIMER_CFG

MCPWM_CAP_TIMER_CFG
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_TIMER_CFG CAP_TIMER_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP_TIMER_EN CAP_SYNCI_EN CAP_SYNCI_SEL CAP_SYNC_SW

CAP_TIMER_EN :
bits : 0 - 0 (1 bit)

CAP_SYNCI_EN :
bits : 1 - 1 (1 bit)

CAP_SYNCI_SEL :
bits : 2 - 4 (3 bit)

CAP_SYNC_SW :
bits : 5 - 5 (1 bit)


CAP_TIMER_PHASE

MCPWM_CAP_TIMER_PHASE
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_TIMER_PHASE CAP_TIMER_PHASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP_PHASE

CAP_PHASE :
bits : 0 - 31 (32 bit)


CAP_CH0_CFG

MCPWM_CAP_CH0_CFG
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_CH0_CFG CAP_CH0_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_EN CAP0_MODE CAP0_PRESCALE CAP0_IN_INVERT CAP0_SW

CAP0_EN :
bits : 0 - 0 (1 bit)

CAP0_MODE :
bits : 1 - 2 (2 bit)

CAP0_PRESCALE :
bits : 3 - 10 (8 bit)

CAP0_IN_INVERT :
bits : 11 - 11 (1 bit)

CAP0_SW :
bits : 12 - 12 (1 bit)


CAP_CH1_CFG

MCPWM_CAP_CH1_CFG
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_CH1_CFG CAP_CH1_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP1_EN CAP1_MODE CAP1_PRESCALE CAP1_IN_INVERT CAP1_SW

CAP1_EN :
bits : 0 - 0 (1 bit)

CAP1_MODE :
bits : 1 - 2 (2 bit)

CAP1_PRESCALE :
bits : 3 - 10 (8 bit)

CAP1_IN_INVERT :
bits : 11 - 11 (1 bit)

CAP1_SW :
bits : 12 - 12 (1 bit)


CAP_CH2_CFG

MCPWM_CAP_CH2_CFG
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_CH2_CFG CAP_CH2_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP2_EN CAP2_MODE CAP2_PRESCALE CAP2_IN_INVERT CAP2_SW

CAP2_EN :
bits : 0 - 0 (1 bit)

CAP2_MODE :
bits : 1 - 2 (2 bit)

CAP2_PRESCALE :
bits : 3 - 10 (8 bit)

CAP2_IN_INVERT :
bits : 11 - 11 (1 bit)

CAP2_SW :
bits : 12 - 12 (1 bit)


CAP_CH0

MCPWM_CAP_CH0
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP_CH0 CAP_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_VALUE

CAP0_VALUE :
bits : 0 - 31 (32 bit)



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