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DPORT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTL

EDGE_INT_ENABLE


CTL

DPORT_CTL
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPORT_CTL_DOUBLE_CLK

DPORT_CTL_DOUBLE_CLK :
bits : 0 - 0 (1 bit)
access : read-write


EDGE_INT_ENABLE

EDGE_INT_ENABLE
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EDGE_INT_ENABLE EDGE_INT_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register wdt_edge_int_enable timer1_edge_int_enable

Register :
bits : 0 - 31 (32 bit)
access : read-write

wdt_edge_int_enable : Enable the watchdog timer edge interrupt
bits : 0 - 0 (1 bit)

timer1_edge_int_enable : Enable the timer1 edge interrupt
bits : 1 - 1 (1 bit)



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