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I2S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x160 byte (0x0)
mem_usage : registers
protection : not protected

Registers

I2STXFIFO

I2SINT_ST

I2SINT_ENA

I2SINT_CLR

I2STIMING

FIFO_CONF

I2SRXEOF_NUM

I2SCONF_SIGLE_DATA

I2SRXFIFO

I2SCONF

I2SINT_RAW


I2STXFIFO

I2STXFIFO
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2STXFIFO I2STXFIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


I2SINT_ST

I2SINT_ST
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SINT_ST I2SINT_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_RX_TAKE_DATA_INT_ST I2S_I2S_TX_PUT_DATA_INT_ST I2S_I2S_RX_WFULL_INT_ST I2S_I2S_RX_REMPTY_INT_ST I2S_I2S_TX_WFULL_INT_ST I2S_I2S_TX_REMPTY_INT_ST

I2S_I2S_RX_TAKE_DATA_INT_ST :
bits : 0 - 0 (1 bit)
access : read-write

I2S_I2S_TX_PUT_DATA_INT_ST :
bits : 1 - 1 (1 bit)
access : read-write

I2S_I2S_RX_WFULL_INT_ST :
bits : 2 - 2 (1 bit)
access : read-write

I2S_I2S_RX_REMPTY_INT_ST :
bits : 3 - 3 (1 bit)
access : read-write

I2S_I2S_TX_WFULL_INT_ST :
bits : 4 - 4 (1 bit)
access : read-write

I2S_I2S_TX_REMPTY_INT_ST :
bits : 5 - 5 (1 bit)
access : read-write


I2SINT_ENA

I2SINT_ENA
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SINT_ENA I2SINT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_RX_TAKE_DATA_INT_ENA I2S_I2S_TX_PUT_DATA_INT_ENA I2S_I2S_RX_WFULL_INT_ENA I2S_I2S_RX_REMPTY_INT_ENA I2S_I2S_TX_WFULL_INT_ENA I2S_I2S_TX_REMPTY_INT_ENA

I2S_I2S_RX_TAKE_DATA_INT_ENA :
bits : 0 - 0 (1 bit)
access : read-write

I2S_I2S_TX_PUT_DATA_INT_ENA :
bits : 1 - 1 (1 bit)
access : read-write

I2S_I2S_RX_WFULL_INT_ENA :
bits : 2 - 2 (1 bit)
access : read-write

I2S_I2S_RX_REMPTY_INT_ENA :
bits : 3 - 3 (1 bit)
access : read-write

I2S_I2S_TX_WFULL_INT_ENA :
bits : 4 - 4 (1 bit)
access : read-write

I2S_I2S_TX_REMPTY_INT_ENA :
bits : 5 - 5 (1 bit)
access : read-write


I2SINT_CLR

I2SINT_CLR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SINT_CLR I2SINT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_TAKE_DATA_INT_CLR I2S_I2S_PUT_DATA_INT_CLR I2S_I2S_RX_WFULL_INT_CLR I2S_I2S_RX_REMPTY_INT_CLR I2S_I2S_TX_WFULL_INT_CLR I2S_I2S_TX_REMPTY_INT_CLR

I2S_I2S_TAKE_DATA_INT_CLR :
bits : 0 - 0 (1 bit)
access : read-write

I2S_I2S_PUT_DATA_INT_CLR :
bits : 1 - 1 (1 bit)
access : read-write

I2S_I2S_RX_WFULL_INT_CLR :
bits : 2 - 2 (1 bit)
access : read-write

I2S_I2S_RX_REMPTY_INT_CLR :
bits : 3 - 3 (1 bit)
access : read-write

I2S_I2S_TX_WFULL_INT_CLR :
bits : 4 - 4 (1 bit)
access : read-write

I2S_I2S_TX_REMPTY_INT_CLR :
bits : 5 - 5 (1 bit)
access : read-write


I2STIMING

I2STIMING
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2STIMING I2STIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_TRANS_BCK_IN_DELAY I2S_TRANS_WS_IN_DELAY I2S_RECE_BCK_IN_DELAY I2S_RECE_WS_IN_DELAY I2S_RECE_SD_IN_DELAY I2S_TRANS_BCK_OUT_DELAY I2S_TRANS_WS_OUT_DELAY I2S_TRANS_SD_OUT_DELAY I2S_RECE_WS_OUT_DELAY I2S_RECE_BCK_OUT_DELAY I2S_TRANS_DSYNC_SW I2S_RECE_DSYNC_SW I2S_TRANS_BCK_IN_INV

I2S_TRANS_BCK_IN_DELAY :
bits : 0 - 1 (2 bit)
access : read-write

I2S_TRANS_WS_IN_DELAY :
bits : 2 - 3 (2 bit)
access : read-write

I2S_RECE_BCK_IN_DELAY :
bits : 4 - 5 (2 bit)
access : read-write

I2S_RECE_WS_IN_DELAY :
bits : 6 - 7 (2 bit)
access : read-write

I2S_RECE_SD_IN_DELAY :
bits : 8 - 9 (2 bit)
access : read-write

I2S_TRANS_BCK_OUT_DELAY :
bits : 10 - 11 (2 bit)
access : read-write

I2S_TRANS_WS_OUT_DELAY :
bits : 12 - 13 (2 bit)
access : read-write

I2S_TRANS_SD_OUT_DELAY :
bits : 14 - 15 (2 bit)
access : read-write

I2S_RECE_WS_OUT_DELAY :
bits : 16 - 17 (2 bit)
access : read-write

I2S_RECE_BCK_OUT_DELAY :
bits : 18 - 19 (2 bit)
access : read-write

I2S_TRANS_DSYNC_SW :
bits : 20 - 20 (1 bit)
access : read-write

I2S_RECE_DSYNC_SW :
bits : 21 - 21 (1 bit)
access : read-write

I2S_TRANS_BCK_IN_INV :
bits : 22 - 22 (1 bit)
access : read-write


FIFO_CONF

I2S_FIFO_CONF
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_CONF FIFO_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_RX_DATA_NUM I2S_I2S_TX_DATA_NUM I2S_I2S_DSCR_EN I2S_I2S_TX_FIFO_MOD I2S_I2S_RX_FIFO_MOD

I2S_I2S_RX_DATA_NUM :
bits : 0 - 5 (6 bit)
access : read-write

I2S_I2S_TX_DATA_NUM :
bits : 6 - 11 (6 bit)
access : read-write

I2S_I2S_DSCR_EN :
bits : 12 - 12 (1 bit)
access : read-write

I2S_I2S_TX_FIFO_MOD :
bits : 13 - 15 (3 bit)
access : read-write

I2S_I2S_RX_FIFO_MOD :
bits : 16 - 18 (3 bit)
access : read-write


I2SRXEOF_NUM

I2SRXEOF_NUM
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SRXEOF_NUM I2SRXEOF_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_RX_EOF_NUM

I2S_I2S_RX_EOF_NUM :
bits : 0 - 31 (32 bit)
access : read-write


I2SCONF_SIGLE_DATA

I2SCONF_SIGLE_DATA
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCONF_SIGLE_DATA I2SCONF_SIGLE_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_SIGLE_DATA

I2S_I2S_SIGLE_DATA :
bits : 0 - 31 (32 bit)
access : read-write


I2SRXFIFO

I2SRXFIFO
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SRXFIFO I2SRXFIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


I2SCONF

I2SCONF
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCONF I2SCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_TX_RESET I2S_I2S_RX_RESET I2S_I2S_TX_FIFO_RESET I2S_I2S_RX_FIFO_RESET I2S_TRANS_SLAVE_MOD I2S_RECE_SLAVE_MOD I2S_RIGHT_FIRST I2S_MSB_RIGHT I2S_I2S_TX_START I2S_I2S_RX_START I2S_TRANS_MSB_SHIFT I2S_RECE_MSB_SHIFT I2S_BITS_MOD I2S_CLKM_DIV_NUM I2S_BCK_DIV_NUM

I2S_I2S_TX_RESET :
bits : 0 - 0 (1 bit)
access : read-write

I2S_I2S_RX_RESET :
bits : 1 - 1 (1 bit)
access : read-write

I2S_I2S_TX_FIFO_RESET :
bits : 2 - 2 (1 bit)
access : read-write

I2S_I2S_RX_FIFO_RESET :
bits : 3 - 3 (1 bit)
access : read-write

I2S_TRANS_SLAVE_MOD :
bits : 4 - 4 (1 bit)
access : read-write

I2S_RECE_SLAVE_MOD :
bits : 5 - 5 (1 bit)
access : read-write

I2S_RIGHT_FIRST :
bits : 6 - 6 (1 bit)
access : read-write

I2S_MSB_RIGHT :
bits : 7 - 7 (1 bit)
access : read-write

I2S_I2S_TX_START :
bits : 8 - 8 (1 bit)
access : read-write

I2S_I2S_RX_START :
bits : 9 - 9 (1 bit)
access : read-write

I2S_TRANS_MSB_SHIFT :
bits : 10 - 10 (1 bit)
access : read-write

I2S_RECE_MSB_SHIFT :
bits : 11 - 11 (1 bit)
access : read-write

I2S_BITS_MOD :
bits : 12 - 15 (4 bit)
access : read-write

I2S_CLKM_DIV_NUM :
bits : 16 - 21 (6 bit)
access : read-write

I2S_BCK_DIV_NUM :
bits : 22 - 27 (6 bit)
access : read-write


I2SINT_RAW

I2SINT_RAW
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SINT_RAW I2SINT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_I2S_RX_TAKE_DATA_INT_RAW I2S_I2S_TX_PUT_DATA_INT_RAW I2S_I2S_RX_WFULL_INT_RAW I2S_I2S_RX_REMPTY_INT_RAW I2S_I2S_TX_WFULL_INT_RAW I2S_I2S_TX_REMPTY_INT_RAW

I2S_I2S_RX_TAKE_DATA_INT_RAW :
bits : 0 - 0 (1 bit)
access : read-write

I2S_I2S_TX_PUT_DATA_INT_RAW :
bits : 1 - 1 (1 bit)
access : read-write

I2S_I2S_RX_WFULL_INT_RAW :
bits : 2 - 2 (1 bit)
access : read-write

I2S_I2S_RX_REMPTY_INT_RAW :
bits : 3 - 3 (1 bit)
access : read-write

I2S_I2S_TX_WFULL_INT_RAW :
bits : 4 - 4 (1 bit)
access : read-write

I2S_I2S_TX_REMPTY_INT_RAW :
bits : 5 - 5 (1 bit)
access : read-write



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