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SLC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONF0

INT_CLR

RX_STATUS

RX_FIFO_PUSH

TX_STATUS

TX_FIFO_POP

RX_LINK

TX_LINK

INTVEC_TOHOST

TOKEN0

TOKEN1

CONF1

STATE0

INT_RAW

STATE1

BRIDGE_CONF

RX_EOF_DES_ADDR

TX_EOF_DES_ADDR

RX_EOF_BFR_DES_ADDR

AHB_TEST

SDIO_ST

RX_DSCR_CONF

TXLINK_DSCR

TXLINK_DSCR_BF0

TXLINK_DSCR_BF1

RXLINK_DSCR

RXLINK_DSCR_BF0

RXLINK_DSCR_BF1

DATE

ID

INT_STATUS

INT_ENA


CONF0

SLC_CONF0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF0 CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TXLINK_RST SLC_RXLINK_RST SLC_AHBM_FIFO_RST SLC_AHBM_RST SLC_TX_LOOP_TEST SLC_RX_LOOP_TEST SLC_RX_AUTO_WRBACK SLC_RX_NO_RESTART_CLR SLC_DSCR_BURST_EN SLC_DATA_BURST_EN SLC_MODE

SLC_TXLINK_RST :
bits : 0 - 0 (1 bit)
access : read-write

SLC_RXLINK_RST :
bits : 1 - 1 (1 bit)
access : read-write

SLC_AHBM_FIFO_RST :
bits : 2 - 2 (1 bit)
access : read-write

SLC_AHBM_RST :
bits : 3 - 3 (1 bit)
access : read-write

SLC_TX_LOOP_TEST :
bits : 4 - 4 (1 bit)
access : read-write

SLC_RX_LOOP_TEST :
bits : 5 - 5 (1 bit)
access : read-write

SLC_RX_AUTO_WRBACK :
bits : 6 - 6 (1 bit)
access : read-write

SLC_RX_NO_RESTART_CLR :
bits : 7 - 7 (1 bit)
access : read-write

SLC_DSCR_BURST_EN :
bits : 8 - 8 (1 bit)
access : read-write

SLC_DATA_BURST_EN :
bits : 9 - 9 (1 bit)
access : read-write

SLC_MODE :
bits : 12 - 13 (2 bit)
access : read-write


INT_CLR

SLC_INT_CLR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_FRHOST_BIT0_INT_CLR SLC_FRHOST_BIT1_INT_CLR SLC_FRHOST_BIT2_INT_CLR SLC_FRHOST_BIT3_INT_CLR SLC_FRHOST_BIT4_INT_CLR SLC_FRHOST_BIT5_INT_CLR SLC_FRHOST_BIT6_INT_CLR SLC_FRHOST_BIT7_INT_CLR SLC_RX_START_INT_CLR SLC_TX_START_INT_CLR SLC_RX_UDF_INT_CLR SLC_TX_OVF_INT_CLR SLC_TOKEN0_1TO0_INT_CLR SLC_TOKEN1_1TO0_INT_CLR SLC_TX_DONE_INT_CLR SLC_TX_EOF_INT_CLR SLC_RX_DONE_INT_CLR SLC_RX_EOF_INT_CLR SLC_TOHOST_INT_CLR SLC_TX_DSCR_ERR_INT_CLR SLC_RX_DSCR_ERR_INT_CLR SLC_TX_DSCR_EMPTY_INT_CLR

SLC_FRHOST_BIT0_INT_CLR :
bits : 0 - 0 (1 bit)
access : read-write

SLC_FRHOST_BIT1_INT_CLR :
bits : 1 - 1 (1 bit)
access : read-write

SLC_FRHOST_BIT2_INT_CLR :
bits : 2 - 2 (1 bit)
access : read-write

SLC_FRHOST_BIT3_INT_CLR :
bits : 3 - 3 (1 bit)
access : read-write

SLC_FRHOST_BIT4_INT_CLR :
bits : 4 - 4 (1 bit)
access : read-write

SLC_FRHOST_BIT5_INT_CLR :
bits : 5 - 5 (1 bit)
access : read-write

SLC_FRHOST_BIT6_INT_CLR :
bits : 6 - 6 (1 bit)
access : read-write

SLC_FRHOST_BIT7_INT_CLR :
bits : 7 - 7 (1 bit)
access : read-write

SLC_RX_START_INT_CLR :
bits : 8 - 8 (1 bit)
access : read-write

SLC_TX_START_INT_CLR :
bits : 9 - 9 (1 bit)
access : read-write

SLC_RX_UDF_INT_CLR :
bits : 10 - 10 (1 bit)
access : read-write

SLC_TX_OVF_INT_CLR :
bits : 11 - 11 (1 bit)
access : read-write

SLC_TOKEN0_1TO0_INT_CLR :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TOKEN1_1TO0_INT_CLR :
bits : 13 - 13 (1 bit)
access : read-write

SLC_TX_DONE_INT_CLR :
bits : 14 - 14 (1 bit)
access : read-write

SLC_TX_EOF_INT_CLR :
bits : 15 - 15 (1 bit)
access : read-write

SLC_RX_DONE_INT_CLR :
bits : 16 - 16 (1 bit)
access : read-write

SLC_RX_EOF_INT_CLR :
bits : 17 - 17 (1 bit)
access : read-write

SLC_TOHOST_INT_CLR :
bits : 18 - 18 (1 bit)
access : read-write

SLC_TX_DSCR_ERR_INT_CLR :
bits : 19 - 19 (1 bit)
access : read-write

SLC_RX_DSCR_ERR_INT_CLR :
bits : 20 - 20 (1 bit)
access : read-write

SLC_TX_DSCR_EMPTY_INT_CLR :
bits : 21 - 21 (1 bit)
access : read-write


RX_STATUS

SLC_RX_STATUS
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_STATUS RX_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_RX_FULL SLC_RX_EMPTY

SLC_RX_FULL :
bits : 0 - 0 (1 bit)
access : read-write

SLC_RX_EMPTY :
bits : 1 - 1 (1 bit)
access : read-write


RX_FIFO_PUSH

SLC_RX_FIFO_PUSH
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_FIFO_PUSH RX_FIFO_PUSH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_RXFIFO_WDATA SLC_RXFIFO_PUSH

SLC_RXFIFO_WDATA :
bits : 0 - 8 (9 bit)
access : read-write

SLC_RXFIFO_PUSH :
bits : 16 - 16 (1 bit)
access : read-write


TX_STATUS

SLC_TX_STATUS
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_STATUS TX_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TX_FULL SLC_TX_EMPTY

SLC_TX_FULL :
bits : 0 - 0 (1 bit)
access : read-write

SLC_TX_EMPTY :
bits : 1 - 1 (1 bit)
access : read-write


TX_FIFO_POP

SLC_TX_FIFO_POP
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FIFO_POP TX_FIFO_POP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TXFIFO_RDATA SLC_TXFIFO_POP

SLC_TXFIFO_RDATA :
bits : 0 - 10 (11 bit)
access : read-write

SLC_TXFIFO_POP :
bits : 16 - 16 (1 bit)
access : read-write


SLC_RX_LINK
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_LINK RX_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_RXLINK_ADDR SLC_RXLINK_STOP SLC_RXLINK_START SLC_RXLINK_RESTART SLC_RXLINK_PARK

SLC_RXLINK_ADDR :
bits : 0 - 19 (20 bit)
access : read-write

SLC_RXLINK_STOP :
bits : 28 - 28 (1 bit)
access : read-write

SLC_RXLINK_START :
bits : 29 - 29 (1 bit)
access : read-write

SLC_RXLINK_RESTART :
bits : 30 - 30 (1 bit)
access : read-write

SLC_RXLINK_PARK :
bits : 31 - 31 (1 bit)
access : read-write


SLC_TX_LINK
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_LINK TX_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TXLINK_ADDR SLC_TXLINK_STOP SLC_TXLINK_START SLC_TXLINK_RESTART SLC_TXLINK_PARK

SLC_TXLINK_ADDR :
bits : 0 - 19 (20 bit)
access : read-write

SLC_TXLINK_STOP :
bits : 28 - 28 (1 bit)
access : read-write

SLC_TXLINK_START :
bits : 29 - 29 (1 bit)
access : read-write

SLC_TXLINK_RESTART :
bits : 30 - 30 (1 bit)
access : read-write

SLC_TXLINK_PARK :
bits : 31 - 31 (1 bit)
access : read-write


INTVEC_TOHOST

SLC_INTVEC_TOHOST
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTVEC_TOHOST INTVEC_TOHOST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TOHOST_INTVEC

SLC_TOHOST_INTVEC :
bits : 0 - 7 (8 bit)
access : read-write


TOKEN0

SLC_TOKEN0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOKEN0 TOKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TOKEN0_LOCAL_WDATA SLC_TOKEN0_LOCAL_WR SLC_TOKEN0_LOCAL_INC SLC_TOKEN0_LOCAL_INC_MORE SLC_TOKEN0

SLC_TOKEN0_LOCAL_WDATA :
bits : 0 - 11 (12 bit)
access : read-write

SLC_TOKEN0_LOCAL_WR :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TOKEN0_LOCAL_INC :
bits : 13 - 13 (1 bit)
access : read-write

SLC_TOKEN0_LOCAL_INC_MORE :
bits : 14 - 14 (1 bit)
access : read-write

SLC_TOKEN0 :
bits : 16 - 27 (12 bit)
access : read-write


TOKEN1

SLC_TOKEN1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOKEN1 TOKEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TOKEN1_LOCAL_WDATA SLC_TOKEN1_LOCAL_WR SLC_TOKEN1_LOCAL_INC SLC_TOKEN1_LOCAL_INC_MORE SLC_TOKEN1

SLC_TOKEN1_LOCAL_WDATA :
bits : 0 - 11 (12 bit)
access : read-write

SLC_TOKEN1_LOCAL_WR :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TOKEN1_LOCAL_INC :
bits : 13 - 13 (1 bit)
access : read-write

SLC_TOKEN1_LOCAL_INC_MORE :
bits : 14 - 14 (1 bit)
access : read-write

SLC_TOKEN1 :
bits : 16 - 27 (12 bit)
access : read-write


CONF1

SLC_CONF1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF1 CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


STATE0

SLC_STATE0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE0 STATE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


INT_RAW

SLC_INT_RAW
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_FRHOST_BIT0_INT_RAW SLC_FRHOST_BIT1_INT_RAW SLC_FRHOST_BIT2_INT_RAW SLC_FRHOST_BIT3_INT_RAW SLC_FRHOST_BIT4_INT_RAW SLC_FRHOST_BIT5_INT_RAW SLC_FRHOST_BIT6_INT_RAW SLC_FRHOST_BIT7_INT_RAW SLC_RX_START_INT_RAW SLC_TX_START_INT_RAW SLC_RX_UDF_INT_RAW SLC_TX_OVF_INT_RAW SLC_TOKEN0_1TO0_INT_RAW SLC_TOKEN1_1TO0_INT_RAW SLC_TX_DONE_INT_RAW SLC_TX_EOF_INT_RAW SLC_RX_DONE_INT_RAW SLC_RX_EOF_INT_RAW SLC_TOHOST_INT_RAW SLC_TX_DSCR_ERR_INT_RAW SLC_RX_DSCR_ERR_INT_RAW SLC_TX_DSCR_EMPTY_INT_RAW

SLC_FRHOST_BIT0_INT_RAW :
bits : 0 - 0 (1 bit)
access : read-write

SLC_FRHOST_BIT1_INT_RAW :
bits : 1 - 1 (1 bit)
access : read-write

SLC_FRHOST_BIT2_INT_RAW :
bits : 2 - 2 (1 bit)
access : read-write

SLC_FRHOST_BIT3_INT_RAW :
bits : 3 - 3 (1 bit)
access : read-write

SLC_FRHOST_BIT4_INT_RAW :
bits : 4 - 4 (1 bit)
access : read-write

SLC_FRHOST_BIT5_INT_RAW :
bits : 5 - 5 (1 bit)
access : read-write

SLC_FRHOST_BIT6_INT_RAW :
bits : 6 - 6 (1 bit)
access : read-write

SLC_FRHOST_BIT7_INT_RAW :
bits : 7 - 7 (1 bit)
access : read-write

SLC_RX_START_INT_RAW :
bits : 8 - 8 (1 bit)
access : read-write

SLC_TX_START_INT_RAW :
bits : 9 - 9 (1 bit)
access : read-write

SLC_RX_UDF_INT_RAW :
bits : 10 - 10 (1 bit)
access : read-write

SLC_TX_OVF_INT_RAW :
bits : 11 - 11 (1 bit)
access : read-write

SLC_TOKEN0_1TO0_INT_RAW :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TOKEN1_1TO0_INT_RAW :
bits : 13 - 13 (1 bit)
access : read-write

SLC_TX_DONE_INT_RAW :
bits : 14 - 14 (1 bit)
access : read-write

SLC_TX_EOF_INT_RAW :
bits : 15 - 15 (1 bit)
access : read-write

SLC_RX_DONE_INT_RAW :
bits : 16 - 16 (1 bit)
access : read-write

SLC_RX_EOF_INT_RAW :
bits : 17 - 17 (1 bit)
access : read-write

SLC_TOHOST_INT_RAW :
bits : 18 - 18 (1 bit)
access : read-write

SLC_TX_DSCR_ERR_INT_RAW :
bits : 19 - 19 (1 bit)
access : read-write

SLC_RX_DSCR_ERR_INT_RAW :
bits : 20 - 20 (1 bit)
access : read-write

SLC_TX_DSCR_EMPTY_INT_RAW :
bits : 21 - 21 (1 bit)
access : read-write


STATE1

SLC_STATE1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE1 STATE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


BRIDGE_CONF

SLC_BRIDGE_CONF
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRIDGE_CONF BRIDGE_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TXEOF_ENA SLC_FIFO_MAP_ENA SLC_TX_DUMMY_MODE SLC_TX_PUSH_IDLE_NUM

SLC_TXEOF_ENA :
bits : 0 - 5 (6 bit)
access : read-write

SLC_FIFO_MAP_ENA :
bits : 8 - 11 (4 bit)
access : read-write

SLC_TX_DUMMY_MODE :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TX_PUSH_IDLE_NUM :
bits : 16 - 31 (16 bit)
access : read-write


RX_EOF_DES_ADDR

SLC_RX_EOF_DES_ADDR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_EOF_DES_ADDR RX_EOF_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


TX_EOF_DES_ADDR

SLC_TX_EOF_DES_ADDR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_EOF_DES_ADDR TX_EOF_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


RX_EOF_BFR_DES_ADDR

SLC_RX_EOF_BFR_DES_ADDR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_EOF_BFR_DES_ADDR RX_EOF_BFR_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


AHB_TEST

SLC_AHB_TEST
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_TEST AHB_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_AHB_TESTMODE SLC_AHB_TESTADDR

SLC_AHB_TESTMODE :
bits : 0 - 2 (3 bit)
access : read-write

SLC_AHB_TESTADDR :
bits : 4 - 5 (2 bit)
access : read-write


SDIO_ST

SLC_SDIO_ST
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDIO_ST SDIO_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_CMD_ST SLC_FUNC_ST SLC_SDIO_WAKEUP SLC_BUS_ST

SLC_CMD_ST :
bits : 0 - 2 (3 bit)
access : read-write

SLC_FUNC_ST :
bits : 4 - 7 (4 bit)
access : read-write

SLC_SDIO_WAKEUP :
bits : 8 - 8 (1 bit)
access : read-write

SLC_BUS_ST :
bits : 12 - 14 (3 bit)
access : read-write


RX_DSCR_CONF

SLC_RX_DSCR_CONF
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_DSCR_CONF RX_DSCR_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_TOKEN_NO_REPLACE SLC_INFOR_NO_REPLACE

SLC_TOKEN_NO_REPLACE :
bits : 8 - 8 (1 bit)
access : read-write

SLC_INFOR_NO_REPLACE :
bits : 9 - 9 (1 bit)
access : read-write


SLC_TXLINK_DSCR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXLINK_DSCR TXLINK_DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


SLC_TXLINK_DSCR_BF0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXLINK_DSCR_BF0 TXLINK_DSCR_BF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


SLC_TXLINK_DSCR_BF1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXLINK_DSCR_BF1 TXLINK_DSCR_BF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


SLC_RXLINK_DSCR
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXLINK_DSCR RXLINK_DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


SLC_RXLINK_DSCR_BF0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXLINK_DSCR_BF0 RXLINK_DSCR_BF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


SLC_RXLINK_DSCR_BF1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXLINK_DSCR_BF1 RXLINK_DSCR_BF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


DATE

SLC_DATE
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


ID

SLC_ID
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register

Register :
bits : 0 - 31 (32 bit)
access : read-write


INT_STATUS

SLC_INT_STATUS
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_FRHOST_BIT0_INT_ST SLC_FRHOST_BIT1_INT_ST SLC_FRHOST_BIT2_INT_ST SLC_FRHOST_BIT3_INT_ST SLC_FRHOST_BIT4_INT_ST SLC_FRHOST_BIT5_INT_ST SLC_FRHOST_BIT6_INT_ST SLC_FRHOST_BIT7_INT_ST SLC_RX_START_INT_ST SLC_TX_START_INT_ST SLC_RX_UDF_INT_ST SLC_TX_OVF_INT_ST SLC_TOKEN0_1TO0_INT_ST SLC_TOKEN1_1TO0_INT_ST SLC_TX_DONE_INT_ST SLC_TX_EOF_INT_ST SLC_RX_DONE_INT_ST SLC_RX_EOF_INT_ST SLC_TOHOST_INT_ST SLC_TX_DSCR_ERR_INT_ST SLC_RX_DSCR_ERR_INT_ST SLC_TX_DSCR_EMPTY_INT_ST

SLC_FRHOST_BIT0_INT_ST :
bits : 0 - 0 (1 bit)
access : read-write

SLC_FRHOST_BIT1_INT_ST :
bits : 1 - 1 (1 bit)
access : read-write

SLC_FRHOST_BIT2_INT_ST :
bits : 2 - 2 (1 bit)
access : read-write

SLC_FRHOST_BIT3_INT_ST :
bits : 3 - 3 (1 bit)
access : read-write

SLC_FRHOST_BIT4_INT_ST :
bits : 4 - 4 (1 bit)
access : read-write

SLC_FRHOST_BIT5_INT_ST :
bits : 5 - 5 (1 bit)
access : read-write

SLC_FRHOST_BIT6_INT_ST :
bits : 6 - 6 (1 bit)
access : read-write

SLC_FRHOST_BIT7_INT_ST :
bits : 7 - 7 (1 bit)
access : read-write

SLC_RX_START_INT_ST :
bits : 8 - 8 (1 bit)
access : read-write

SLC_TX_START_INT_ST :
bits : 9 - 9 (1 bit)
access : read-write

SLC_RX_UDF_INT_ST :
bits : 10 - 10 (1 bit)
access : read-write

SLC_TX_OVF_INT_ST :
bits : 11 - 11 (1 bit)
access : read-write

SLC_TOKEN0_1TO0_INT_ST :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TOKEN1_1TO0_INT_ST :
bits : 13 - 13 (1 bit)
access : read-write

SLC_TX_DONE_INT_ST :
bits : 14 - 14 (1 bit)
access : read-write

SLC_TX_EOF_INT_ST :
bits : 15 - 15 (1 bit)
access : read-write

SLC_RX_DONE_INT_ST :
bits : 16 - 16 (1 bit)
access : read-write

SLC_RX_EOF_INT_ST :
bits : 17 - 17 (1 bit)
access : read-write

SLC_TOHOST_INT_ST :
bits : 18 - 18 (1 bit)
access : read-write

SLC_TX_DSCR_ERR_INT_ST :
bits : 19 - 19 (1 bit)
access : read-write

SLC_RX_DSCR_ERR_INT_ST :
bits : 20 - 20 (1 bit)
access : read-write

SLC_TX_DSCR_EMPTY_INT_ST :
bits : 21 - 21 (1 bit)
access : read-write


INT_ENA

SLC_INT_ENA
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLC_FRHOST_BIT0_INT_ENA SLC_FRHOST_BIT1_INT_ENA SLC_FRHOST_BIT2_INT_ENA SLC_FRHOST_BIT3_INT_ENA SLC_FRHOST_BIT4_INT_ENA SLC_FRHOST_BIT5_INT_ENA SLC_FRHOST_BIT6_INT_ENA SLC_FRHOST_BIT7_INT_ENA SLC_RX_START_INT_ENA SLC_TX_START_INT_ENA SLC_RX_UDF_INT_ENA SLC_TX_OVF_INT_ENA SLC_TOKEN0_1TO0_INT_ENA SLC_TOKEN1_1TO0_INT_ENA SLC_TX_DONE_INT_ENA SLC_TX_EOF_INT_ENA SLC_RX_DONE_INT_ENA SLC_RX_EOF_INT_ENA SLC_TOHOST_INT_ENA SLC_TX_DSCR_ERR_INT_ENA SLC_RX_DSCR_ERR_INT_ENA SLC_TX_DSCR_EMPTY_INT_ENA

SLC_FRHOST_BIT0_INT_ENA :
bits : 0 - 0 (1 bit)
access : read-write

SLC_FRHOST_BIT1_INT_ENA :
bits : 1 - 1 (1 bit)
access : read-write

SLC_FRHOST_BIT2_INT_ENA :
bits : 2 - 2 (1 bit)
access : read-write

SLC_FRHOST_BIT3_INT_ENA :
bits : 3 - 3 (1 bit)
access : read-write

SLC_FRHOST_BIT4_INT_ENA :
bits : 4 - 4 (1 bit)
access : read-write

SLC_FRHOST_BIT5_INT_ENA :
bits : 5 - 5 (1 bit)
access : read-write

SLC_FRHOST_BIT6_INT_ENA :
bits : 6 - 6 (1 bit)
access : read-write

SLC_FRHOST_BIT7_INT_ENA :
bits : 7 - 7 (1 bit)
access : read-write

SLC_RX_START_INT_ENA :
bits : 8 - 8 (1 bit)
access : read-write

SLC_TX_START_INT_ENA :
bits : 9 - 9 (1 bit)
access : read-write

SLC_RX_UDF_INT_ENA :
bits : 10 - 10 (1 bit)
access : read-write

SLC_TX_OVF_INT_ENA :
bits : 11 - 11 (1 bit)
access : read-write

SLC_TOKEN0_1TO0_INT_ENA :
bits : 12 - 12 (1 bit)
access : read-write

SLC_TOKEN1_1TO0_INT_ENA :
bits : 13 - 13 (1 bit)
access : read-write

SLC_TX_DONE_INT_ENA :
bits : 14 - 14 (1 bit)
access : read-write

SLC_TX_EOF_INT_ENA :
bits : 15 - 15 (1 bit)
access : read-write

SLC_RX_DONE_INT_ENA :
bits : 16 - 16 (1 bit)
access : read-write

SLC_RX_EOF_INT_ENA :
bits : 17 - 17 (1 bit)
access : read-write

SLC_TOHOST_INT_ENA :
bits : 18 - 18 (1 bit)
access : read-write

SLC_TX_DSCR_ERR_INT_ENA :
bits : 19 - 19 (1 bit)
access : read-write

SLC_RX_DSCR_ERR_INT_ENA :
bits : 20 - 20 (1 bit)
access : read-write

SLC_TX_DSCR_EMPTY_INT_ENA :
bits : 21 - 21 (1 bit)
access : read-write



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