SPI_CMD

SPI_RD_STATUS

SPI_W6

SPI_W7

SPI_CTRL2

SPI_W8

SPI_W9

SPI_CLOCK

SPI_W10

SPI_W11

SPI_USER

SPI_W12

SPI_W13

SPI_USER1

SPI_W14

SPI_W15

SPI_USER2

SPI_WR_STATUS

SPI_PIN

SPI_SLAVE

SPI_SLAVE1

SPI_SLAVE2

SPI_SLAVE3

SPI_ADDR

SPI_W0

SPI_W1

SPI_CTRL

SPI_W2

SPI_W3

SPI_CTRL1

SPI_W4

SPI_W5

SPI_EXT3

spi_usr : In the master mode, it is the start bit of a single operation. Self-clear by hardware
bits : 18 - 18 (1 bit)
access : read-write

spi_hpm :
bits : 19 - 19 (1 bit)

spi_res :
bits : 20 - 20 (1 bit)

spi_dp :
bits : 21 - 21 (1 bit)

spi_ce :
bits : 22 - 22 (1 bit)

spi_be :
bits : 23 - 23 (1 bit)

spi_se :
bits : 24 - 24 (1 bit)

spi_pp :
bits : 25 - 25 (1 bit)

spi_write_sr :
bits : 26 - 26 (1 bit)

spi_read_sr :
bits : 27 - 27 (1 bit)

spi_read_id :
bits : 28 - 28 (1 bit)

spi_write_disable :
bits : 29 - 29 (1 bit)

spi_write_enable :
bits : 30 - 30 (1 bit)

spi_read :
bits : 31 - 31 (1 bit)

slv_rd_status : In the slave mode, this register are the status register for the master to read out.
bits : 0 - 31 (32 bit)
access : read-write

spi_w6 : the data inside the buffer of the SPI module, byte 6
bits : 0 - 31 (32 bit)
access : read-write

spi_w7 : the data inside the buffer of the SPI module, byte 7
bits : 0 - 31 (32 bit)
access : read-write

spi_miso_delay_mode : MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
bits : 16 - 17 (2 bit)
access : read-write

spi_miso_delay_num : MISO signals are delayed by 80MHz clock cycles
bits : 18 - 20 (3 bit)
access : read-write

spi_mosi_delay_mode : MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
bits : 21 - 22 (2 bit)
access : read-write

spi_mosi_delay_num : MOSI signals are delayed by 80MHz clock cycles
bits : 23 - 25 (3 bit)
access : read-write

spi_cs_delay_mode : spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
bits : 26 - 27 (2 bit)
access : read-write

spi_cs_delay_num : spi_cs signal is delayed by 80MHz clock cycles
bits : 28 - 31 (4 bit)
access : read-write

spi_w8 : the data inside the buffer of the SPI module, byte 8
bits : 0 - 31 (32 bit)
access : read-write

spi_w9 : the data inside the buffer of the SPI module, byte 9
bits : 0 - 31 (32 bit)
access : read-write

spi_clkcnt_L : In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.
bits : 0 - 5 (6 bit)
access : read-write

spi_clkcnt_H : In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.
bits : 6 - 11 (6 bit)
access : read-write

spi_clkcnt_N : In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)
bits : 12 - 17 (6 bit)
access : read-write

spi_clkdiv_pre : In the master mode, it is pre-divider of spi_clk.
bits : 18 - 30 (13 bit)
access : read-write

spi_clk_equ_sysclk : In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
bits : 31 - 31 (1 bit)
access : read-write

spi_w10 : the data inside the buffer of the SPI module, byte 10
bits : 0 - 31 (32 bit)
access : read-write

spi_w11 : the data inside the buffer of the SPI module, byte 11
bits : 0 - 31 (32 bit)
access : read-write

spi_duplex : set spi in full duplex mode
bits : 0 - 0 (1 bit)

spi_ahb_user_command_4byte : reserved
bits : 1 - 1 (1 bit)

spi_flash_mode :
bits : 2 - 2 (1 bit)

spi_ahb_user_command : reserved
bits : 3 - 3 (1 bit)

spi_cs_hold : spi cs keep low when spi is in done phase. 1: enable 0: disable.
bits : 4 - 4 (1 bit)

spi_cs_setup : spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
bits : 5 - 5 (1 bit)

spi_ck_i_edge : In the slave mode, 1: rising-edge; 0: falling-edge
bits : 6 - 6 (1 bit)
access : read-write

spi_ck_o_edge : In the master mode, 1: rising-edge; 0: falling-edge
bits : 7 - 7 (1 bit)

spi_rd_byte_order : In "read-data" (MISO) phase, 1: little-endian; 0: big_endian
bits : 10 - 10 (1 bit)
access : read-write

spi_wr_byte_order : In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian
bits : 11 - 11 (1 bit)
access : read-write

spi_fwrite_dual : In the write operations, "read-data" phase apply 2 signals
bits : 12 - 12 (1 bit)
access : read-write

spi_fwrite_quad : In the write operations, "read-data" phase apply 4 signals
bits : 13 - 13 (1 bit)
access : read-write

spi_fwrite_dio : In the write operations, "address" phase and "read-data" phase apply 2 signals
bits : 14 - 14 (1 bit)
access : read-write

spi_fwrite_qio : In the write operations, "address" phase and "read-data" phase apply 4 signals
bits : 15 - 15 (1 bit)
access : read-write

spi_sio : 1: mosi and miso signals share the same pin
bits : 16 - 16 (1 bit)
access : read-write

reg_usr_miso_highpart : 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15
bits : 24 - 24 (1 bit)
access : read-write

reg_usr_mosi_highpart : 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15
bits : 25 - 25 (1 bit)
access : read-write

spi_usr_mosi : This bit enable the "write-data" phase of an operation.
bits : 27 - 27 (1 bit)
access : read-write

spi_usr_miso : This bit enable the "read-data" phase of an operation.
bits : 28 - 28 (1 bit)
access : read-write

spi_usr_dummy : This bit enable the "dummy" phase of an operation.
bits : 29 - 29 (1 bit)
access : read-write

spi_usr_addr : This bit enable the "address" phase of an operation.
bits : 30 - 30 (1 bit)
access : read-write

spi_usr_command : This bit enable the "command" phase of an operation.
bits : 31 - 31 (1 bit)
access : read-write

spi_w12 : the data inside the buffer of the SPI module, byte 12
bits : 0 - 31 (32 bit)
access : read-write

spi_w13 : the data inside the buffer of the SPI module, byte 13
bits : 0 - 31 (32 bit)
access : read-write

reg_usr_dummy_cyclelen : The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1)
bits : 0 - 7 (8 bit)
access : read-write

reg_usr_miso_bitlen : The length in bits of "read-data" phase. The register value shall be (bit_num-1)
bits : 8 - 16 (9 bit)
access : read-write

reg_usr_mosi_bitlen : The length in bits of "write-data" phase. The register value shall be (bit_num-1)
bits : 17 - 25 (9 bit)
access : read-write

reg_usr_addr_bitlen : The length in bits of "address" phase. The register value shall be (bit_num-1)
bits : 26 - 31 (6 bit)
access : read-write

spi_w14 : the data inside the buffer of the SPI module, byte 14
bits : 0 - 31 (32 bit)
access : read-write

spi_w15 : the data inside the buffer of the SPI module, byte 15
bits : 0 - 31 (32 bit)
access : read-write

reg_usr_command_value : The value of "command" phase
bits : 0 - 15 (16 bit)
access : read-write

reg_usr_command_bitlen : The length in bits of "command" phase. The register value shall be (bit_num-1)
bits : 28 - 31 (4 bit)
access : read-write

slv_wr_status : In the slave mode, this register are the status register for the master to write into.
bits : 0 - 31 (32 bit)
access : read-write

spi_cs0_dis : 1: disable CS0; 0: spi_cs signal is from/to CS0 pin
bits : 0 - 0 (1 bit)
access : read-write

spi_cs1_dis : 1: disable CS1; 0: spi_cs signal is from/to CS1 pin
bits : 1 - 1 (1 bit)
access : read-write

spi_cs2_dis : 1: disable CS2; 0: spi_cs signal is from/to CS2 pin
bits : 2 - 2 (1 bit)
access : read-write

spi_idle_edge : In the master mode, 1: high when idle; 0: low when idle
bits : 29 - 29 (1 bit)

slv_rd_buf_done : The interrupt raw bit for the completement of "read-buffer" operation in the slave mode.
bits : 0 - 0 (1 bit)
access : read-write

slv_wr_buf_done : The interrupt raw bit for the completement of "write-buffer" operation in the slave mode.
bits : 1 - 1 (1 bit)
access : read-write

slv_rd_sta_done : The interrupt raw bit for the completement of "read-status" operation in the slave mode.
bits : 2 - 2 (1 bit)
access : read-write

slv_wr_sta_done : The interrupt raw bit for the completement of "write-status" operation in the slave mode.
bits : 3 - 3 (1 bit)
access : read-write

spi_trans_done : The interrupt raw bit for the completement of any operation in both the master mode and the slave mode.
bits : 4 - 4 (1 bit)
access : read-write

spi_int_en : Interrupt enable bits for the below 5 sources
bits : 5 - 9 (5 bit)
access : read-write

spi_trans_cnt : The operations counter in both the master mode and the slave mode.
bits : 23 - 26 (4 bit)
access : read-only

slv_cmd_define : 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".
bits : 27 - 27 (1 bit)
access : read-write

spi_slave_mode : 1: slave mode, 0: master mode.
bits : 30 - 30 (1 bit)
access : read-write

spi_sync_reset : It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
bits : 31 - 31 (1 bit)
access : read-write

slv_rdbuf_dummy_en : In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations.
bits : 0 - 0 (1 bit)
access : read-write

slv_wrbuf_dummy_en : In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations.
bits : 1 - 1 (1 bit)
access : read-write

slv_rdsta_dummy_en : In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations.
bits : 2 - 2 (1 bit)
access : read-write

slv_wrsta_dummy_en : In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations.
bits : 3 - 3 (1 bit)
access : read-write

slv_wr_addr_bitlen : In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1)
bits : 4 - 9 (6 bit)
access : read-write

slv_rd_addr_bitlen : In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1)
bits : 10 - 15 (6 bit)
access : read-write

slv_buf_bitlen : In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1)
bits : 16 - 24 (9 bit)
access : read-write

slv_status_bitlen : In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
bits : 27 - 31 (5 bit)
access : read-write

slv_rdsta_dummy_cyclelen : In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1)
bits : 0 - 7 (8 bit)
access : read-write

slv_wrsta_dummy_cyclelen : In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1)
bits : 8 - 15 (8 bit)
access : read-write

slv_rdbuf_dummy_cyclelen : In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1)
bits : 16 - 23 (8 bit)
access : read-write

slv_wrbuf_dummy_cyclelen : In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
bits : 24 - 31 (8 bit)
access : read-write

slv_rdbuf_cmd_value : In slave mode, it is the value of "read-buffer" command
bits : 0 - 7 (8 bit)
access : read-write

slv_wrbuf_cmd_value : In slave mode, it is the value of "write-buffer" command
bits : 8 - 15 (8 bit)
access : read-write

slv_rdsta_cmd_value : In slave mode, it is the value of "read-status" command
bits : 16 - 23 (8 bit)
access : read-write

slv_wrsta_cmd_value : In slave mode, it is the value of "write-status" command
bits : 24 - 31 (8 bit)
access : read-write

iodata_start_addr : In the master mode, it is the value of address in "address" phase.
bits : 0 - 31 (32 bit)
access : read-write

address :
bits : 0 - 23 (24 bit)

size :
bits : 24 - 31 (8 bit)

spi_w0 : the data inside the buffer of the SPI module, byte 0
bits : 0 - 31 (32 bit)
access : read-write

spi_w1 : the data inside the buffer of the SPI module, byte 1
bits : 0 - 31 (32 bit)
access : read-write

spi_fastrd_mode : this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode
bits : 13 - 13 (1 bit)
access : read-write

spi_dout_mode : In the read operations, "read-data" phase apply 2 signals
bits : 14 - 14 (1 bit)
access : read-write

spi_qout_mode : In the read operations, "read-data" phase apply 4 signals
bits : 20 - 20 (1 bit)
access : read-write

spi_dio_mode : In the read operations, "address" phase and "read-data" phase apply 2 signals
bits : 23 - 23 (1 bit)
access : read-write

spi_qio_mode : In the read operations, "address" phase and "read-data" phase apply 4 signals
bits : 24 - 24 (1 bit)
access : read-write

spi_rd_bit_order : In "read-data" (MISO) phase, 1: LSB first; 0: MSB first
bits : 25 - 25 (1 bit)
access : read-write

spi_wr_bit_order : In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first
bits : 26 - 26 (1 bit)
access : read-write

spi_w2 : the data inside the buffer of the SPI module, byte 2
bits : 0 - 31 (32 bit)
access : read-write

spi_w3 : the data inside the buffer of the SPI module, byte 3
bits : 0 - 31 (32 bit)
access : read-write

status : In the slave mode, it is the status for master to read out.
bits : 0 - 15 (16 bit)

wb_mode : Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.
bits : 16 - 23 (8 bit)

status_ext : In the slave mode,it is the status for master to read out.
bits : 24 - 31 (8 bit)

spi_w4 : the data inside the buffer of the SPI module, byte 4
bits : 0 - 31 (32 bit)
access : read-write

spi_w5 : the data inside the buffer of the SPI module, byte 5
bits : 0 - 31 (32 bit)
access : read-write

reg_int_hold_ena : This register is for two SPI masters to share the same cs, clock and data signals.
bits : 0 - 1 (2 bit)
access : read-write