UART_FIFO

UART_INT_CLR

UART_CLKDIV

UART_AUTOBAUD

UART_STATUS

UART_CONF0

UART_CONF1

UART_LOWPULSE

UART_HIGHPULSE

UART_RXD_CNT

UART_INT_RAW

UART_DATE

UART_ID

UART_INT_ST

UART_INT_ENA

rxfifo_rd_byte : R/W share the same address
bits : 0 - 7 (8 bit)
access : read-only

rxfifo_write_byte : R/W share the same address
bits : 0 - 7 (8 bit)

rxfifo_full_int_clr : Set this bit to clear the rx fifo full interrupt
bits : 0 - 0 (1 bit)
access : write-only

txfifo_empty_int_clr : Set this bit to clear the tx fifo empty interrupt
bits : 1 - 1 (1 bit)
access : write-only

parity_err_int_clr : Set this bit to clear the parity error interrupt
bits : 2 - 2 (1 bit)
access : write-only

frm_err_int_clr : Set this bit to clear other rx error interrupt
bits : 3 - 3 (1 bit)
access : write-only

rxfifo_ovf_int_clr : Set this bit to clear the rx fifo over-flow interrupt
bits : 4 - 4 (1 bit)
access : write-only

dsr_chg_int_clr : Set this bit to clear the DSR changing interrupt
bits : 5 - 5 (1 bit)
access : write-only

cts_chg_int_clr : Set this bit to clear the CTS changing interrupt
bits : 6 - 6 (1 bit)
access : write-only

brk_det_int_clr : Set this bit to clear the rx byte start interrupt
bits : 7 - 7 (1 bit)
access : write-only

rxfifo_tout_int_clr : Set this bit to clear the rx time-out interrupt
bits : 8 - 8 (1 bit)
access : write-only

uart_clkdiv : BAUDRATE = UART_CLK_FREQ / UART_CLKDIV
bits : 0 - 19 (20 bit)
access : read-write

autobaud_en : Set this bit to enable baudrate detect
bits : 0 - 0 (1 bit)
access : read-write

glitch_filt :
bits : 8 - 15 (8 bit)
access : read-write

rxfifo_cnt : Number of data in uart rx fifo
bits : 0 - 7 (8 bit)
access : read-only

dsrn : The level of uart dsr pin
bits : 13 - 13 (1 bit)
access : read-only

ctsn : The level of uart cts pin
bits : 14 - 14 (1 bit)
access : read-only

rxd : The level of uart rxd pin
bits : 15 - 15 (1 bit)
access : read-only

txfifo_cnt : Number of data in UART TX fifo
bits : 16 - 23 (8 bit)
access : read-only

dtrn : The level of uart dtr pin
bits : 29 - 29 (1 bit)
access : read-only

rtsn : The level of uart rts pin
bits : 30 - 30 (1 bit)
access : read-only

txd : The level of the uart txd pin
bits : 31 - 31 (1 bit)
access : read-only

parity : Set parity check: 0:even 1:odd, UART CONFIG1
bits : 0 - 0 (1 bit)
access : read-write

parity_en : Set this bit to enable uart parity check
bits : 1 - 1 (1 bit)
access : read-write

bit_num : Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits
bits : 2 - 3 (2 bit)
access : read-write

stop_bit_num : Set stop bit: 1:1bit 2:1.5bits 3:2bits
bits : 4 - 5 (2 bit)
access : read-write

sw_rts : sw rts
bits : 6 - 6 (1 bit)
access : read-write

sw_dtr : sw dtr
bits : 7 - 7 (1 bit)
access : read-write

txd_brk : RESERVED, DO NOT CHANGE THIS BIT
bits : 8 - 8 (1 bit)
access : read-write

uart_loopback : Set this bit to enable uart loopback test mode
bits : 14 - 14 (1 bit)
access : read-write

tx_flow_en : Set this bit to enable uart tx hardware flow control
bits : 15 - 15 (1 bit)
access : read-write

rxfifo_rst : Set this bit to reset uart rx fifo
bits : 17 - 17 (1 bit)
access : read-write

txfifo_rst : Set this bit to reset uart tx fifo
bits : 18 - 18 (1 bit)
access : read-write

uart_rxd_inv : Set this bit to inverse uart rxd level
bits : 19 - 19 (1 bit)
access : read-write

uart_cts_inv : Set this bit to inverse uart cts level
bits : 20 - 20 (1 bit)
access : read-write

uart_dsr_inv : Set this bit to inverse uart dsr level
bits : 21 - 21 (1 bit)
access : read-write

uart_txd_inv : Set this bit to inverse uart txd level
bits : 22 - 22 (1 bit)
access : read-write

uart_rts_inv : Set this bit to inverse uart rts level
bits : 23 - 23 (1 bit)
access : read-write

uart_dtr_inv : Set this bit to inverse uart dtr level
bits : 24 - 24 (1 bit)
access : read-write

rxfifo_full_thrhd : The config bits for rx fifo full threshold,0-127
bits : 0 - 6 (7 bit)
access : read-write

txfifo_empty_thrhd : The config bits for tx fifo empty threshold,0-127
bits : 8 - 14 (7 bit)
access : read-write

rx_flow_thrhd : The config bits for rx flow control threshold,0-127
bits : 16 - 22 (7 bit)
access : read-write

rx_flow_en : Set this bit to enable rx hardware flow control
bits : 23 - 23 (1 bit)
access : read-write

rx_tout_thrhd : Config bits for rx time-out threshold,uint: byte,0-127
bits : 24 - 30 (7 bit)
access : read-write

rx_tout_en : Set this bit to enable rx time-out function
bits : 31 - 31 (1 bit)
access : read-write

lowpulse_min_cnt : used in baudrate detect
bits : 0 - 19 (20 bit)
access : read-only

highpulse_min_cnt : used in baudrate detect
bits : 0 - 19 (20 bit)
access : read-only

rxd_edge_cnt : used in baudrate detect
bits : 0 - 9 (10 bit)
access : read-only

rxfifo_full_int_raw : The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)
bits : 0 - 0 (1 bit)
access : read-only

txfifo_empty_int_raw : The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)
bits : 1 - 1 (1 bit)
access : read-only

parity_err_int_raw : The interrupt raw bit for parity check error
bits : 2 - 2 (1 bit)
access : read-only

frm_err_int_raw : The interrupt raw bit for other rx error
bits : 3 - 3 (1 bit)
access : read-only

rxfifo_ovf_int_raw : The interrupt raw bit for rx fifo overflow
bits : 4 - 4 (1 bit)
access : read-only

dsr_chg_int_raw : The interrupt raw bit for DSR changing level
bits : 5 - 5 (1 bit)
access : read-only

cts_chg_int_raw : The interrupt raw bit for CTS changing level
bits : 6 - 6 (1 bit)
access : read-only

brk_det_int_raw : The interrupt raw bit for Rx byte start error
bits : 7 - 7 (1 bit)
access : read-only

rxfifo_tout_int_raw : The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)
bits : 8 - 8 (1 bit)
access : read-only

uart_date : UART HW INFO
bits : 0 - 31 (32 bit)
access : read-write

uart_id :
bits : 0 - 31 (32 bit)
access : read-write

rxfifo_full_int_st : The interrupt state bit for RX fifo full event
bits : 0 - 0 (1 bit)
access : read-only

txfifo_empty_int_st : The interrupt state bit for TX fifo empty
bits : 1 - 1 (1 bit)
access : read-only

parity_err_int_st : The interrupt state bit for rx parity error
bits : 2 - 2 (1 bit)
access : read-only

frm_err_int_st : The interrupt state for other rx error
bits : 3 - 3 (1 bit)
access : read-only

rxfifo_ovf_int_st : The interrupt state bit for RX fifo overflow
bits : 4 - 4 (1 bit)
access : read-only

dsr_chg_int_st : The interrupt state bit for DSR changing level
bits : 5 - 5 (1 bit)
access : read-only

cts_chg_int_st : The interrupt state bit for CTS changing level
bits : 6 - 6 (1 bit)
access : read-only

brk_det_int_st : The interrupt state bit for rx byte start error
bits : 7 - 7 (1 bit)
access : read-only

rxfifo_tout_int_st : The interrupt state bit for Rx time-out event
bits : 8 - 8 (1 bit)
access : read-only

rxfifo_full_int_ena : The interrupt enable bit for rx fifo full event
bits : 0 - 0 (1 bit)
access : read-write

txfifo_empty_int_ena : The interrupt enable bit for tx fifo empty event
bits : 1 - 1 (1 bit)
access : read-write

parity_err_int_ena : The interrupt enable bit for parity error
bits : 2 - 2 (1 bit)
access : read-write

frm_err_int_ena : The interrupt enable bit for other rx error
bits : 3 - 3 (1 bit)
access : read-write

rxfifo_ovf_int_ena : The interrupt enable bit for rx fifo overflow
bits : 4 - 4 (1 bit)
access : read-write

dsr_chg_int_ena : The interrupt enable bit for DSR changing level
bits : 5 - 5 (1 bit)
access : read-write

cts_chg_int_ena : The interrupt enable bit for CTS changing level
bits : 6 - 6 (1 bit)
access : read-write

brk_det_int_ena : The interrupt enable bit for rx byte start error
bits : 7 - 7 (1 bit)
access : read-write

rxfifo_tout_int_ena : The interrupt enable bit for rx time-out interrupt
bits : 8 - 8 (1 bit)
access : read-write