Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
CNT_STRUCT[1]-CNT_STRUCT[0]-CTL
CNT_STRUCT[1]-CNT_STRUCT[0]-CNT
CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CTL
CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CNT
CNT_STRUCT[3]-CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CTL
CNT_STRUCT[3]-CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CNT
CNT_STRUCT[4]-CNT_STRUCT[3]-CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CTL
CNT_STRUCT[4]-CNT_STRUCT[3]-CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CNT
CNT_STRUCT[5]-CNT_STRUCT[4]-CNT_STRUCT[3]-CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CTL
CNT_STRUCT[5]-CNT_STRUCT[4]-CNT_STRUCT[3]-CNT_STRUCT[2]-CNT_STRUCT[1]-CNT_STRUCT[0]-CNT
Profile control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIN_MODE : Specifies the profiling time window mode: '0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs. In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped. '1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect.
bits : 0 - 0 (1 bit)
access : read-write
ENABLED : Enables the profiling block: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile command
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_TR : Software start trigger for the profiling time window. When written with '1', the profiling time window is started. Can only be used in start / stop mode (PROFILE_WIN_MODE=0). Has no effect in enable mode (PROFILE_WIN_MODE=1).
bits : 0 - 0 (1 bit)
access : read-write
STOP_TR : Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped. Can only be used in start / stop mode (PROFILE_WIN_MODE=0). Has no effect in enable mode (PROFILE_WIN_MODE=1).
bits : 1 - 2 (2 bit)
access : read-write
CLR_ALL_CNT : Counter clear. When written with '1', all profiling counter registers are cleared to 0x00.
bits : 8 - 16 (9 bit)
access : read-write
Profile counter configuration
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile counter configuration
address_offset : 0x1830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x1838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile counter configuration
address_offset : 0x2060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x2068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile counter configuration
address_offset : 0x28A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x28A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile counter configuration
address_offset : 0x30F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x30F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile counter configuration
address_offset : 0x3950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x3958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WIN_ACTIVE : Indicates if the profiling time window is active. '0': Not active. '1': Active.
bits : 0 - 0 (1 bit)
access : read-only
Profile counter configuration
address_offset : 0x41C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x41C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
Profile interrupt
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_OVFLW : This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter. SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0').
bits : 0 - 31 (32 bit)
access : read-write
Profile interrupt set
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_OVFLW : SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register.
bits : 0 - 31 (32 bit)
access : read-write
Profile interrupt mask
address_offset : 0x7C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_OVFLW : Mask bit for corresponding field in the INTR register.
bits : 0 - 31 (32 bit)
access : read-write
Profile interrupt masked
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT_OVFLW : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 31 (32 bit)
access : read-only
Profile counter configuration
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_DURATION : This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.
bits : 0 - 0 (1 bit)
access : read-write
REF_CLK_SEL : This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CLK_TIMER
Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
1 : CLK_IMO
IMO - Internal Main Oscillator
2 : CLK_ECO
ECO - External-Crystal Oscillator
3 : CLK_LF
Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
4 : CLK_HF
High frequuency clock ('clk_hfx').
5 : CLK_PERI
Peripheral clock ('clk_peri').
6 : RSVD_6
N/A
7 : RSVD_7
N/A
End of enumeration elements list.
MON_SEL : This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.
bits : 16 - 38 (23 bit)
access : read-write
ENABLED : Enables the profiling counter: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Profile counter value
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.
bits : 0 - 31 (32 bit)
access : read-write
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