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address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
LPCOMP Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPREF_EN : Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) - 1: IP enabled
bits : 31 - 62 (32 bit)
access : read-write
LPCOMP Interrupt request register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
COMP1 : Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
LPCOMP Interrupt set register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
COMP1 : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
LPCOMP Interrupt request mask
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
COMP1_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
LPCOMP Interrupt request masked
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP0_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
COMP1_MASKED : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
LPCOMP Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OUT0 : Current output value of the comparator 0.
bits : 0 - 0 (1 bit)
access : read-only
OUT1 : Current output value of the comparator 1.
bits : 16 - 32 (17 bit)
access : read-only
Comparator 0 control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE0 : Operating mode for the comparator
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Off
1 : ULP
Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used.
2 : LP
Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used.
3 : NORMAL
Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used.
End of enumeration elements list.
HYST0 : Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis
bits : 5 - 10 (6 bit)
access : read-write
INTTYPE0 : Sets which edge will trigger an IRQ
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled, no interrupts will be detected
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
DSI_BYPASS0 : Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.
bits : 10 - 20 (11 bit)
access : read-write
DSI_LEVEL0 : Synchronous comparator DSI (trigger) output : 0=pulse, 1=level
bits : 11 - 22 (12 bit)
access : read-write
Comparator 0 switch control
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0_IP0 : Comparator 0 positive terminal isolation switch to GPIO
bits : 0 - 0 (1 bit)
access : read-write
CMP0_AP0 : Comparator 0 positive terminal switch to amuxbusA
bits : 1 - 2 (2 bit)
access : read-write
CMP0_BP0 : Comparator 0 positive terminal switch to amuxbusB
bits : 2 - 4 (3 bit)
access : read-write
CMP0_IN0 : Comparator 0 negative terminal isolation switch to GPIO
bits : 4 - 8 (5 bit)
access : read-write
CMP0_AN0 : Comparator 0 negative terminal switch to amuxbusA
bits : 5 - 10 (6 bit)
access : read-write
CMP0_BN0 : Comparator 0 negative terminal switch to amuxbusB
bits : 6 - 12 (7 bit)
access : read-write
CMP0_VN0 : Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set)
bits : 7 - 14 (8 bit)
access : read-write
Comparator 0 switch control clear
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0_IP0 : see corresponding bit in CMP0_SW
bits : 0 - 0 (1 bit)
access : read-write
CMP0_AP0 : see corresponding bit in CMP0_SW
bits : 1 - 2 (2 bit)
access : read-write
CMP0_BP0 : see corresponding bit in CMP0_SW
bits : 2 - 4 (3 bit)
access : read-write
CMP0_IN0 : see corresponding bit in CMP0_SW
bits : 4 - 8 (5 bit)
access : read-write
CMP0_AN0 : see corresponding bit in CMP0_SW
bits : 5 - 10 (6 bit)
access : read-write
CMP0_BN0 : see corresponding bit in CMP0_SW
bits : 6 - 12 (7 bit)
access : read-write
CMP0_VN0 : see corresponding bit in CMP0_SW
bits : 7 - 14 (8 bit)
access : read-write
Comparator 1 control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE1 : Operating mode for the comparator
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Off
1 : ULP
Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used.
2 : LP
Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used.
3 : NORMAL
Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used.
End of enumeration elements list.
HYST1 : Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis
bits : 5 - 10 (6 bit)
access : read-write
INTTYPE1 : Sets which edge will trigger an IRQ
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled, no interrupts will be detected
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
DSI_BYPASS1 : Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.
bits : 10 - 20 (11 bit)
access : read-write
DSI_LEVEL1 : Synchronous comparator DSI (trigger) output : 0=pulse, 1=level
bits : 11 - 22 (12 bit)
access : read-write
Comparator 1 switch control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1_IP1 : Comparator 1 positive terminal isolation switch to GPIO
bits : 0 - 0 (1 bit)
access : read-write
CMP1_AP1 : Comparator 1 positive terminal switch to amuxbusA
bits : 1 - 2 (2 bit)
access : read-write
CMP1_BP1 : Comparator 1 positive terminal switch to amuxbusB
bits : 2 - 4 (3 bit)
access : read-write
CMP1_IN1 : Comparator 1 negative terminal isolation switch to GPIO
bits : 4 - 8 (5 bit)
access : read-write
CMP1_AN1 : Comparator 1 negative terminal switch to amuxbusA
bits : 5 - 10 (6 bit)
access : read-write
CMP1_BN1 : Comparator 1 negative terminal switch to amuxbusB
bits : 6 - 12 (7 bit)
access : read-write
CMP1_VN1 : Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set)
bits : 7 - 14 (8 bit)
access : read-write
Comparator 1 switch control clear
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1_IP1 : see corresponding bit in CMP1_SW
bits : 0 - 0 (1 bit)
access : read-write
CMP1_AP1 : see corresponding bit in CMP1_SW
bits : 1 - 2 (2 bit)
access : read-write
CMP1_BP1 : see corresponding bit in CMP1_SW
bits : 2 - 4 (3 bit)
access : read-write
CMP1_IN1 : see corresponding bit in CMP1_SW
bits : 4 - 8 (5 bit)
access : read-write
CMP1_AN1 : see corresponding bit in CMP1_SW
bits : 5 - 10 (6 bit)
access : read-write
CMP1_BN1 : see corresponding bit in CMP1_SW
bits : 6 - 12 (7 bit)
access : read-write
CMP1_VN1 : see corresponding bit in CMP1_SW
bits : 7 - 14 (8 bit)
access : read-write
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