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address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_ENABLED : Enables the I2S TX component: '0': Disabled. '1': Enabled.
bits : 30 - 60 (31 bit)
access : read-write
RX_ENABLED : Enables the I2S RX component: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLOCK_DIV : Frequency divisor for generating I2S clock frequency. The selected clock with CLOCK_SEL is divided by this. '0': Bypass '1': 2 x '2': 3 x '3': 4 x ... '62': 63 x '63': 64 x
bits : 0 - 5 (6 bit)
access : read-write
CLOCK_SEL : Selects clock to be used by I2S: '0': Internal clock ('clk_audio_i2s') '1': External clock ('clk_i2s_if')
bits : 8 - 16 (9 bit)
access : read-write
Command
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_START : Transmitter enable: '0': Disabled. '1': Enabled.
bits : 0 - 0 (1 bit)
access : read-write
TX_PAUSE : Pause enable: '0': Disabled (TX FIFO data is sent over I2S). '1': Enabled ('0' data is sent over I2S, instead of TX FIFO data).
bits : 8 - 16 (9 bit)
access : read-write
RX_START : Receiver enable: '0': Disabled. '1': Enabled.
bits : 16 - 32 (17 bit)
access : read-write
TX FIFO control
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGGER_LEVEL : Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated.
bits : 0 - 7 (8 bit)
access : read-write
CLEAR : When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
bits : 16 - 32 (17 bit)
access : read-write
FREEZE : When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes.
bits : 17 - 34 (18 bit)
access : read-write
TX FIFO status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USED : Number of entries in the TX FIFO. The field value is in the range [0, 256].
bits : 0 - 8 (9 bit)
access : read-only
RD_PTR : TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes.
bits : 16 - 39 (24 bit)
access : read-only
WR_PTR : TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes.
bits : 24 - 55 (32 bit)
access : read-only
TX FIFO write
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'.
bits : 0 - 31 (32 bit)
access : write-only
RX FIFO control
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGGER_LEVEL : Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)].
bits : 0 - 7 (8 bit)
access : read-write
CLEAR : When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
bits : 16 - 32 (17 bit)
access : read-write
FREEZE : When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee.
bits : 17 - 34 (18 bit)
access : read-write
RX FIFO status
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USED : Number of entries in the RX FIFO. The field value is in the range [0, 256].
bits : 0 - 8 (9 bit)
access : read-only
RD_PTR : RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes.
bits : 16 - 39 (24 bit)
access : read-only
WR_PTR : RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes.
bits : 24 - 55 (32 bit)
access : read-only
RX FIFO read
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. Notes: - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data.
bits : 0 - 31 (32 bit)
access : read-only
RX FIFO silent read
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. Notes: - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data.
bits : 0 - 31 (32 bit)
access : read-only
Trigger control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_REQ_EN : Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission '0': Disabled. '1': Enabled.
bits : 0 - 0 (1 bit)
access : read-write
RX_REQ_EN : Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception '0': Disabled. '1': Enabled.
bits : 16 - 32 (17 bit)
access : read-write
Transmitter control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B_CLOCK_INV : Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'. 1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge 2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1) 3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge 4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3) (Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. Note: When Master mode, must be '0'. (Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV)
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : FALLING_EDGE_TX
SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0
1 : RISING_EDGE_TX
SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0
End of enumeration elements list.
CH_NR : Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CH_NUM1
1 channel
1 : CH_NUM2
2 channels
2 : CH_NUM3
3 channels
3 : CH_NUM4
4 channels
4 : CH_NUM5
5 channels
5 : CH_NUM6
6 channels
6 : CH_NUM7
7 channels
7 : CH_NUM8
8 channels
End of enumeration elements list.
MS : Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_MS)
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : SLAVE
Slave
1 : MASTER
Master
End of enumeration elements list.
I2S_MODE : Select I2S, left-justified or TDM: (Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : LEFT_JUSTIFIED
Left Justified
1 : I2S
I2S mode
2 : TDM_A
TDM mode A, the 1st Channel align to WSO
Rising Edge
3 : TDM_B
TDM mode B, the 1st Channel align to WSO
Rising edge with1 SCK Delay
End of enumeration elements list.
WS_PULSE : Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) Note: When not TDM mode, must be '1'.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : SCK_PERIOD
Pulse width is 1 SCK period
1 : CH_LENGTH
Pulse width is 1 channel length
End of enumeration elements list.
OVHDATA : Set overhead value: '0': Set to '0' '1': Set to '1' (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)
bits : 12 - 24 (13 bit)
access : read-write
WD_EN : Set watchdog for 'tx_ws_in': '0': Disabled. '1': Enabled.
bits : 13 - 26 (14 bit)
access : read-write
CH_LEN : Channel length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN)
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : BIT_LEN8
8-bit
1 : BIT_LEN16
16-bit
2 : BIT_LEN18
18-bit
3 : BIT_LEN20
20-bit
4 : BIT_LEN24
24-bit
5 : BIT_LEN32
32-bit
End of enumeration elements list.
WORD_LEN : Word length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - Don't configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.TX_CFG.TX_IWL)
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : BIT_LEN8
8-bit
1 : BIT_LEN16
16-bit
2 : BIT_LEN18
18-bit
3 : BIT_LEN20
20-bit
4 : BIT_LEN24
24-bit
5 : BIT_LEN32
32-bit
End of enumeration elements list.
SCKO_POL : TX master bit clock polarity. When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. '0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge '1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge
bits : 24 - 48 (25 bit)
access : read-write
SCKI_POL : TX slave bit clock polarity. When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details.
bits : 25 - 50 (26 bit)
access : read-write
Transmitter watchdog
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_COUNTER : Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'.
bits : 0 - 31 (32 bit)
access : read-write
Receiver control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B_CLOCK_INV : Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'. 1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge 2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1) 3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge 4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3) (Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. Note: When Slave mode, must be '0'. (Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV)
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE_RX
SDI received at SCK rising edge when RX_CTL.SCKO_POL=0
1 : FALLING_EDGE_RX
SDI received at SCK falling edge when RX_CTL.SCKO_POL=0
End of enumeration elements list.
CH_NR : Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : CH_NUM1
1 channel
1 : CH_NUM2
2 channels
2 : CH_NUM3
3 channels
3 : CH_NUM4
4 channels
4 : CH_NUM5
5 channels
5 : CH_NUM6
6 channels
6 : CH_NUM7
7 channels
7 : CH_NUM8
8 channels
End of enumeration elements list.
MS : Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.RX_MS)
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : SLAVE
Slave
1 : MASTER
Master
End of enumeration elements list.
I2S_MODE : Select I2S, left-justified or TDM: (Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : LEFT_JUSTIFIED
Left Justified
1 : I2S
I2S mode
2 : TDM_A
TDM mode A, the 1st Channel align to WSO
Rising Edge
3 : TDM_B
TDM mode B, the 1st Channel align to WSO
Rising edge with1 SCK Delay
End of enumeration elements list.
WS_PULSE : Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) Note: When not TDM mode, must be '1'.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : SCK_PERIOD
Pulse width is 1 SCK period
1 : CH_LENGTH
Pulse width is 1 channel length
End of enumeration elements list.
WD_EN : Set watchdog for 'rx_ws_in' '0': Disabled. '1': Enabled.
bits : 13 - 26 (14 bit)
access : read-write
CH_LEN : Channel length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN)
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : BIT_LEN8
8-bit
1 : BIT_LEN16
16-bit
2 : BIT_LEN18
18-bit
3 : BIT_LEN20
20-bit
4 : BIT_LEN24
24-bit
5 : BIT_LEN32
32-bit
End of enumeration elements list.
WORD_LEN : Word length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - Don't configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.RX_CFG.RX_IWL)
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : BIT_LEN8
8-bit
1 : BIT_LEN16
16-bit
2 : BIT_LEN18
18-bit
3 : BIT_LEN20
20-bit
4 : BIT_LEN24
24-bit
5 : BIT_LEN32
32-bit
End of enumeration elements list.
BIT_EXTENSION : When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. '0': Extended by '0' '1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')
bits : 23 - 46 (24 bit)
access : read-write
SCKO_POL : RX master bit clock polarity. When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details.
bits : 24 - 48 (25 bit)
access : read-write
SCKI_POL : RX slave bit clock polarity. When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting. '0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge '1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge
bits : 25 - 50 (26 bit)
access : read-write
Receiver watchdog
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_COUNTER : Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'.
bits : 0 - 31 (32 bit)
access : read-write
Interrupt register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_TRIGGER : Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL.
bits : 0 - 0 (1 bit)
access : read-write
TX_NOT_FULL : TX FIFO is not full.
bits : 1 - 2 (2 bit)
access : read-write
TX_EMPTY : TX FIFO is empty; i.e. it has 0 entries.
bits : 4 - 8 (5 bit)
access : read-write
TX_OVERFLOW : Attempt to write to a full TX FIFO.
bits : 5 - 10 (6 bit)
access : read-write
TX_UNDERFLOW : Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'.
bits : 6 - 12 (7 bit)
access : read-write
TX_WD : Triggers (sets to '1') when the Tx watchdog event occurs.
bits : 8 - 16 (9 bit)
access : read-write
RX_TRIGGER : More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL.
bits : 16 - 32 (17 bit)
access : read-write
RX_NOT_EMPTY : RX FIFO is not empty.
bits : 18 - 36 (19 bit)
access : read-write
RX_FULL : RX FIFO is full.
bits : 19 - 38 (20 bit)
access : read-write
RX_OVERFLOW : Attempt to write to a full RX FIFO.
bits : 21 - 42 (22 bit)
access : read-write
RX_UNDERFLOW : Attempt to read from an empty RX FIFO.
bits : 22 - 44 (23 bit)
access : read-write
RX_WD : Triggers (sets to '1') when the Rx watchdog event occurs.
bits : 24 - 48 (25 bit)
access : read-write
Interrupt set register
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_TRIGGER : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
TX_NOT_FULL : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
TX_EMPTY : Write with '1' to set corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
TX_OVERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write
TX_UNDERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 6 - 12 (7 bit)
access : read-write
TX_WD : Write with '1' to set corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write
RX_TRIGGER : Write with '1' to set corresponding bit in interrupt request register.
bits : 16 - 32 (17 bit)
access : read-write
RX_NOT_EMPTY : Write with '1' to set corresponding bit in interrupt request register.
bits : 18 - 36 (19 bit)
access : read-write
RX_FULL : Write with '1' to set corresponding bit in interrupt request register.
bits : 19 - 38 (20 bit)
access : read-write
RX_OVERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 21 - 42 (22 bit)
access : read-write
RX_UNDERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 22 - 44 (23 bit)
access : read-write
RX_WD : Write with '1' to set corresponding bit in interrupt request register.
bits : 24 - 48 (25 bit)
access : read-write
Interrupt mask register
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_TRIGGER : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
TX_NOT_FULL : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
TX_EMPTY : Mask bit for corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
TX_OVERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write
TX_UNDERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 6 - 12 (7 bit)
access : read-write
TX_WD : Mask bit for corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write
RX_TRIGGER : Mask bit for corresponding bit in interrupt request register.
bits : 16 - 32 (17 bit)
access : read-write
RX_NOT_EMPTY : Mask bit for corresponding bit in interrupt request register.
bits : 18 - 36 (19 bit)
access : read-write
RX_FULL : Mask bit for corresponding bit in interrupt request register.
bits : 19 - 38 (20 bit)
access : read-write
RX_OVERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 21 - 42 (22 bit)
access : read-write
RX_UNDERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 22 - 44 (23 bit)
access : read-write
RX_WD : Mask bit for corresponding bit in interrupt request register.
bits : 24 - 48 (25 bit)
access : read-write
Interrupt masked register
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_TRIGGER : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
TX_NOT_FULL : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TX_EMPTY : Logical and of corresponding request and mask bits.
bits : 4 - 8 (5 bit)
access : read-only
TX_OVERFLOW : Logical and of corresponding request and mask bits.
bits : 5 - 10 (6 bit)
access : read-only
TX_UNDERFLOW : Logical and of corresponding request and mask bits.
bits : 6 - 12 (7 bit)
access : read-only
TX_WD : Logical and of corresponding request and mask bits.
bits : 8 - 16 (9 bit)
access : read-only
RX_TRIGGER : Logical and of corresponding request and mask bits.
bits : 16 - 32 (17 bit)
access : read-only
RX_NOT_EMPTY : Logical and of corresponding request and mask bits.
bits : 18 - 36 (19 bit)
access : read-only
RX_FULL : Logical and of corresponding request and mask bits.
bits : 19 - 38 (20 bit)
access : read-only
RX_OVERFLOW : Logical and of corresponding request and mask bits.
bits : 21 - 42 (22 bit)
access : read-only
RX_UNDERFLOW : Logical and of corresponding request and mask bits.
bits : 22 - 44 (23 bit)
access : read-only
RX_WD : Logical and of corresponding request and mask bits.
bits : 24 - 48 (25 bit)
access : read-only
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