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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

LISR

S0CR

S0NDTR

S0PAR

S0M0AR

S0M1AR

S0FCR

S1CR

S1NDTR

S1PAR

S1M0AR

S1M1AR

S1FCR

HISR

S2CR

S2NDTR

S2PAR

S2M0AR

S2M1AR

S2FCR

S3CR

S3NDTR

S3PAR

S3M0AR

S3M1AR

S3FCR

S4CR

S4NDTR

S4PAR

S4M0AR

LIFCR

S4M1AR

S4FCR

S5CR

S5NDTR

S5PAR

S5M0AR

S5M1AR

S5FCR

S6CR

S6NDTR

S6PAR

S6M0AR

S6M1AR

S6FCR

S7CR

S7NDTR

HIFCR

S7PAR

S7M0AR

S7M1AR

S7FCR


LISR

low interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LISR LISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEIF0 DMEIF0 TEIF0 HTIF0 TCIF0 FEIF1 DMEIF1 TEIF1 HTIF1 TCIF1 FEIF2 DMEIF2 TEIF2 HTIF2 TCIF2 FEIF3 DMEIF3 TEIF3 HTIF3 TCIF3

FEIF0 : Stream x FIFO error interrupt flag (x=3..0)
bits : 0 - 0 (1 bit)

DMEIF0 : Stream x direct mode error interrupt flag (x=3..0)
bits : 2 - 2 (1 bit)

TEIF0 : Stream x transfer error interrupt flag (x=3..0)
bits : 3 - 3 (1 bit)

HTIF0 : Stream x half transfer interrupt flag (x=3..0)
bits : 4 - 4 (1 bit)

TCIF0 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 5 - 5 (1 bit)

FEIF1 : Stream x FIFO error interrupt flag (x=3..0)
bits : 6 - 6 (1 bit)

DMEIF1 : Stream x direct mode error interrupt flag (x=3..0)
bits : 8 - 8 (1 bit)

TEIF1 : Stream x transfer error interrupt flag (x=3..0)
bits : 9 - 9 (1 bit)

HTIF1 : Stream x half transfer interrupt flag (x=3..0)
bits : 10 - 10 (1 bit)

TCIF1 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 11 - 11 (1 bit)

FEIF2 : Stream x FIFO error interrupt flag (x=3..0)
bits : 16 - 16 (1 bit)

DMEIF2 : Stream x direct mode error interrupt flag (x=3..0)
bits : 18 - 18 (1 bit)

TEIF2 : Stream x transfer error interrupt flag (x=3..0)
bits : 19 - 19 (1 bit)

HTIF2 : Stream x half transfer interrupt flag (x=3..0)
bits : 20 - 20 (1 bit)

TCIF2 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 21 - 21 (1 bit)

FEIF3 : Stream x FIFO error interrupt flag (x=3..0)
bits : 22 - 22 (1 bit)

DMEIF3 : Stream x direct mode error interrupt flag (x=3..0)
bits : 24 - 24 (1 bit)

TEIF3 : Stream x transfer error interrupt flag (x=3..0)
bits : 25 - 25 (1 bit)

HTIF3 : Stream x half transfer interrupt flag (x=3..0)
bits : 26 - 26 (1 bit)

TCIF3 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 27 - 27 (1 bit)


S0CR

stream x configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S0CR S0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S0NDTR

stream x number of data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S0NDTR S0NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S0PAR

stream x peripheral address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S0PAR S0PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S0M0AR

stream x memory 0 address register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S0M0AR S0M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S0M1AR

stream x memory 1 address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S0M1AR S0M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S0FCR

stream x FIFO control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S0FCR S0FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


S1CR

stream x configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S1CR S1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S1NDTR

stream x number of data register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S1NDTR S1NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S1PAR

stream x peripheral address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S1PAR S1PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S1M0AR

stream x memory 0 address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S1M0AR S1M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S1M1AR

stream x memory 1 address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S1M1AR S1M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S1FCR

stream x FIFO control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S1FCR S1FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


HISR

high interrupt status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HISR HISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEIF4 DMEIF4 TEIF4 HTIF4 TCIF4 FEIF5 DMEIF5 TEIF5 HTIF5 TCIF5 FEIF6 DMEIF6 TEIF6 HTIF6 TCIF6 FEIF7 DMEIF7 TEIF7 HTIF7 TCIF7

FEIF4 : Stream x FIFO error interrupt flag (x=7..4)
bits : 0 - 0 (1 bit)

DMEIF4 : Stream x direct mode error interrupt flag (x=7..4)
bits : 2 - 2 (1 bit)

TEIF4 : Stream x transfer error interrupt flag (x=7..4)
bits : 3 - 3 (1 bit)

HTIF4 : Stream x half transfer interrupt flag (x=7..4)
bits : 4 - 4 (1 bit)

TCIF4 : Stream x transfer complete interrupt flag (x=7..4)
bits : 5 - 5 (1 bit)

FEIF5 : Stream x FIFO error interrupt flag (x=7..4)
bits : 6 - 6 (1 bit)

DMEIF5 : Stream x direct mode error interrupt flag (x=7..4)
bits : 8 - 8 (1 bit)

TEIF5 : Stream x transfer error interrupt flag (x=7..4)
bits : 9 - 9 (1 bit)

HTIF5 : Stream x half transfer interrupt flag (x=7..4)
bits : 10 - 10 (1 bit)

TCIF5 : Stream x transfer complete interrupt flag (x=7..4)
bits : 11 - 11 (1 bit)

FEIF6 : Stream x FIFO error interrupt flag (x=7..4)
bits : 16 - 16 (1 bit)

DMEIF6 : Stream x direct mode error interrupt flag (x=7..4)
bits : 18 - 18 (1 bit)

TEIF6 : Stream x transfer error interrupt flag (x=7..4)
bits : 19 - 19 (1 bit)

HTIF6 : Stream x half transfer interrupt flag (x=7..4)
bits : 20 - 20 (1 bit)

TCIF6 : Stream x transfer complete interrupt flag (x=7..4)
bits : 21 - 21 (1 bit)

FEIF7 : Stream x FIFO error interrupt flag (x=7..4)
bits : 22 - 22 (1 bit)

DMEIF7 : Stream x direct mode error interrupt flag (x=7..4)
bits : 24 - 24 (1 bit)

TEIF7 : Stream x transfer error interrupt flag (x=7..4)
bits : 25 - 25 (1 bit)

HTIF7 : Stream x half transfer interrupt flag (x=7..4)
bits : 26 - 26 (1 bit)

TCIF7 : Stream x transfer complete interrupt flag (x=7..4)
bits : 27 - 27 (1 bit)


S2CR

stream x configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S2CR S2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S2NDTR

stream x number of data register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S2NDTR S2NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S2PAR

stream x peripheral address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S2PAR S2PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S2M0AR

stream x memory 0 address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S2M0AR S2M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S2M1AR

stream x memory 1 address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S2M1AR S2M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S2FCR

stream x FIFO control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S2FCR S2FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


S3CR

stream x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S3CR S3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S3NDTR

stream x number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S3NDTR S3NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S3PAR

stream x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S3PAR S3PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S3M0AR

stream x memory 0 address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S3M0AR S3M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S3M1AR

stream x memory 1 address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S3M1AR S3M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S3FCR

stream x FIFO control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S3FCR S3FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


S4CR

stream x configuration register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S4CR S4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S4NDTR

stream x number of data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S4NDTR S4NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S4PAR

stream x peripheral address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S4PAR S4PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S4M0AR

stream x memory 0 address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S4M0AR S4M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


LIFCR

low interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIFCR LIFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFEIF0 CDMEIF0 CTEIF0 CHTIF0 CTCIF0 CFEIF1 CDMEIF1 CTEIF1 CHTIF1 CTCIF1 CFEIF2 CDMEIF2 CTEIF2 CHTIF2 CTCIF2 CFEIF3 CDMEIF3 CTEIF3 CHTIF3 CTCIF3

CFEIF0 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 0 - 0 (1 bit)

CDMEIF0 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 2 - 2 (1 bit)

CTEIF0 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 3 - 3 (1 bit)

CHTIF0 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 4 - 4 (1 bit)

CTCIF0 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 5 - 5 (1 bit)

CFEIF1 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 6 - 6 (1 bit)

CDMEIF1 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 8 - 8 (1 bit)

CTEIF1 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 9 - 9 (1 bit)

CHTIF1 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 10 - 10 (1 bit)

CTCIF1 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 11 - 11 (1 bit)

CFEIF2 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 16 - 16 (1 bit)

CDMEIF2 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 18 - 18 (1 bit)

CTEIF2 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 19 - 19 (1 bit)

CHTIF2 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 20 - 20 (1 bit)

CTCIF2 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 21 - 21 (1 bit)

CFEIF3 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 22 - 22 (1 bit)

CDMEIF3 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 24 - 24 (1 bit)

CTEIF3 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 25 - 25 (1 bit)

CHTIF3 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 26 - 26 (1 bit)

CTCIF3 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 27 - 27 (1 bit)


S4M1AR

stream x memory 1 address register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S4M1AR S4M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S4FCR

stream x FIFO control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S4FCR S4FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


S5CR

stream x configuration register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S5CR S5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S5NDTR

stream x number of data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S5NDTR S5NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S5PAR

stream x peripheral address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S5PAR S5PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S5M0AR

stream x memory 0 address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S5M0AR S5M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S5M1AR

stream x memory 1 address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S5M1AR S5M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S5FCR

stream x FIFO control register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S5FCR S5FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


S6CR

stream x configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S6CR S6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S6NDTR

stream x number of data register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S6NDTR S6NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


S6PAR

stream x peripheral address register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S6PAR S6PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S6M0AR

stream x memory 0 address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S6M0AR S6M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S6M1AR

stream x memory 1 address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S6M1AR S6M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S6FCR

stream x FIFO control register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S6FCR S6FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write


S7CR

stream x configuration register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S7CR S7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT ACK PBURST MBURST CHSEL

EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)

DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)

TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)

HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)

PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)

DIR : Data transfer direction
bits : 6 - 7 (2 bit)

CIRC : Circular mode
bits : 8 - 8 (1 bit)

PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)

MINC : Memory increment mode
bits : 10 - 10 (1 bit)

PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)

MSIZE : Memory data size
bits : 13 - 14 (2 bit)

PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)

PL : Priority level
bits : 16 - 17 (2 bit)

DBM : Double buffer mode
bits : 18 - 18 (1 bit)

CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)

ACK : ACK
bits : 20 - 20 (1 bit)

PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)

MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)

CHSEL : Channel selection
bits : 25 - 28 (4 bit)


S7NDTR

stream x number of data register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S7NDTR S7NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


HIFCR

high interrupt flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIFCR HIFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFEIF4 CDMEIF4 CTEIF4 CHTIF4 CTCIF4 CFEIF5 CDMEIF5 CTEIF5 CHTIF5 CTCIF5 CFEIF6 CDMEIF6 CTEIF6 CHTIF6 CTCIF6 CFEIF7 CDMEIF7 CTEIF7 CHTIF7 CTCIF7

CFEIF4 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 0 - 0 (1 bit)

CDMEIF4 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 2 - 2 (1 bit)

CTEIF4 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 3 - 3 (1 bit)

CHTIF4 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 4 - 4 (1 bit)

CTCIF4 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 5 - 5 (1 bit)

CFEIF5 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 6 - 6 (1 bit)

CDMEIF5 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 8 - 8 (1 bit)

CTEIF5 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 9 - 9 (1 bit)

CHTIF5 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 10 - 10 (1 bit)

CTCIF5 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 11 - 11 (1 bit)

CFEIF6 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 16 - 16 (1 bit)

CDMEIF6 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 18 - 18 (1 bit)

CTEIF6 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 19 - 19 (1 bit)

CHTIF6 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 20 - 20 (1 bit)

CTCIF6 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 21 - 21 (1 bit)

CFEIF7 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 22 - 22 (1 bit)

CDMEIF7 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 24 - 24 (1 bit)

CTEIF7 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 25 - 25 (1 bit)

CHTIF7 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 26 - 26 (1 bit)

CTCIF7 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 27 - 27 (1 bit)


S7PAR

stream x peripheral address register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S7PAR S7PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


S7M0AR

stream x memory 0 address register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S7M0AR S7M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : Memory 0 address
bits : 0 - 31 (32 bit)


S7M1AR

stream x memory 1 address register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S7M1AR S7M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


S7FCR

stream x FIFO control register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S7FCR S7FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write

FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write



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