\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
low interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEIF0 : Stream x FIFO error interrupt flag (x=3..0)
bits : 0 - 0 (1 bit)
DMEIF0 : Stream x direct mode error interrupt flag (x=3..0)
bits : 2 - 2 (1 bit)
TEIF0 : Stream x transfer error interrupt flag (x=3..0)
bits : 3 - 3 (1 bit)
HTIF0 : Stream x half transfer interrupt flag (x=3..0)
bits : 4 - 4 (1 bit)
TCIF0 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 5 - 5 (1 bit)
FEIF1 : Stream x FIFO error interrupt flag (x=3..0)
bits : 6 - 6 (1 bit)
DMEIF1 : Stream x direct mode error interrupt flag (x=3..0)
bits : 8 - 8 (1 bit)
TEIF1 : Stream x transfer error interrupt flag (x=3..0)
bits : 9 - 9 (1 bit)
HTIF1 : Stream x half transfer interrupt flag (x=3..0)
bits : 10 - 10 (1 bit)
TCIF1 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 11 - 11 (1 bit)
FEIF2 : Stream x FIFO error interrupt flag (x=3..0)
bits : 16 - 16 (1 bit)
DMEIF2 : Stream x direct mode error interrupt flag (x=3..0)
bits : 18 - 18 (1 bit)
TEIF2 : Stream x transfer error interrupt flag (x=3..0)
bits : 19 - 19 (1 bit)
HTIF2 : Stream x half transfer interrupt flag (x=3..0)
bits : 20 - 20 (1 bit)
TCIF2 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 21 - 21 (1 bit)
FEIF3 : Stream x FIFO error interrupt flag (x=3..0)
bits : 22 - 22 (1 bit)
DMEIF3 : Stream x direct mode error interrupt flag (x=3..0)
bits : 24 - 24 (1 bit)
TEIF3 : Stream x transfer error interrupt flag (x=3..0)
bits : 25 - 25 (1 bit)
HTIF3 : Stream x half transfer interrupt flag (x=3..0)
bits : 26 - 26 (1 bit)
TCIF3 : Stream x transfer complete interrupt flag (x = 3..0)
bits : 27 - 27 (1 bit)
stream x configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
stream x configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
high interrupt status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEIF4 : Stream x FIFO error interrupt flag (x=7..4)
bits : 0 - 0 (1 bit)
DMEIF4 : Stream x direct mode error interrupt flag (x=7..4)
bits : 2 - 2 (1 bit)
TEIF4 : Stream x transfer error interrupt flag (x=7..4)
bits : 3 - 3 (1 bit)
HTIF4 : Stream x half transfer interrupt flag (x=7..4)
bits : 4 - 4 (1 bit)
TCIF4 : Stream x transfer complete interrupt flag (x=7..4)
bits : 5 - 5 (1 bit)
FEIF5 : Stream x FIFO error interrupt flag (x=7..4)
bits : 6 - 6 (1 bit)
DMEIF5 : Stream x direct mode error interrupt flag (x=7..4)
bits : 8 - 8 (1 bit)
TEIF5 : Stream x transfer error interrupt flag (x=7..4)
bits : 9 - 9 (1 bit)
HTIF5 : Stream x half transfer interrupt flag (x=7..4)
bits : 10 - 10 (1 bit)
TCIF5 : Stream x transfer complete interrupt flag (x=7..4)
bits : 11 - 11 (1 bit)
FEIF6 : Stream x FIFO error interrupt flag (x=7..4)
bits : 16 - 16 (1 bit)
DMEIF6 : Stream x direct mode error interrupt flag (x=7..4)
bits : 18 - 18 (1 bit)
TEIF6 : Stream x transfer error interrupt flag (x=7..4)
bits : 19 - 19 (1 bit)
HTIF6 : Stream x half transfer interrupt flag (x=7..4)
bits : 20 - 20 (1 bit)
TCIF6 : Stream x transfer complete interrupt flag (x=7..4)
bits : 21 - 21 (1 bit)
FEIF7 : Stream x FIFO error interrupt flag (x=7..4)
bits : 22 - 22 (1 bit)
DMEIF7 : Stream x direct mode error interrupt flag (x=7..4)
bits : 24 - 24 (1 bit)
TEIF7 : Stream x transfer error interrupt flag (x=7..4)
bits : 25 - 25 (1 bit)
HTIF7 : Stream x half transfer interrupt flag (x=7..4)
bits : 26 - 26 (1 bit)
TCIF7 : Stream x transfer complete interrupt flag (x=7..4)
bits : 27 - 27 (1 bit)
stream x configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
stream x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
stream x configuration register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
low interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEIF0 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 0 - 0 (1 bit)
CDMEIF0 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 2 - 2 (1 bit)
CTEIF0 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 3 - 3 (1 bit)
CHTIF0 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 4 - 4 (1 bit)
CTCIF0 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 5 - 5 (1 bit)
CFEIF1 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 6 - 6 (1 bit)
CDMEIF1 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 8 - 8 (1 bit)
CTEIF1 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 9 - 9 (1 bit)
CHTIF1 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 10 - 10 (1 bit)
CTCIF1 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 11 - 11 (1 bit)
CFEIF2 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 16 - 16 (1 bit)
CDMEIF2 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 18 - 18 (1 bit)
CTEIF2 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 19 - 19 (1 bit)
CHTIF2 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 20 - 20 (1 bit)
CTCIF2 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 21 - 21 (1 bit)
CFEIF3 : Stream x clear FIFO error interrupt flag (x = 3..0)
bits : 22 - 22 (1 bit)
CDMEIF3 : Stream x clear direct mode error interrupt flag (x = 3..0)
bits : 24 - 24 (1 bit)
CTEIF3 : Stream x clear transfer error interrupt flag (x = 3..0)
bits : 25 - 25 (1 bit)
CHTIF3 : Stream x clear half transfer interrupt flag (x = 3..0)
bits : 26 - 26 (1 bit)
CTCIF3 : Stream x clear transfer complete interrupt flag (x = 3..0)
bits : 27 - 27 (1 bit)
stream x memory 1 address register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
stream x configuration register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
stream x configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
stream x peripheral address register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
stream x configuration register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Stream enable / flag stream ready when read low
bits : 0 - 0 (1 bit)
DMEIE : Direct mode error interrupt enable
bits : 1 - 1 (1 bit)
TEIE : Transfer error interrupt enable
bits : 2 - 2 (1 bit)
HTIE : Half transfer interrupt enable
bits : 3 - 3 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 4 - 4 (1 bit)
PFCTRL : Peripheral flow controller
bits : 5 - 5 (1 bit)
DIR : Data transfer direction
bits : 6 - 7 (2 bit)
CIRC : Circular mode
bits : 8 - 8 (1 bit)
PINC : Peripheral increment mode
bits : 9 - 9 (1 bit)
MINC : Memory increment mode
bits : 10 - 10 (1 bit)
PSIZE : Peripheral data size
bits : 11 - 12 (2 bit)
MSIZE : Memory data size
bits : 13 - 14 (2 bit)
PINCOS : Peripheral increment offset size
bits : 15 - 15 (1 bit)
PL : Priority level
bits : 16 - 17 (2 bit)
DBM : Double buffer mode
bits : 18 - 18 (1 bit)
CT : Current target (only in double buffer mode)
bits : 19 - 19 (1 bit)
ACK : ACK
bits : 20 - 20 (1 bit)
PBURST : Peripheral burst transfer configuration
bits : 21 - 22 (2 bit)
MBURST : Memory burst transfer configuration
bits : 23 - 24 (2 bit)
CHSEL : Channel selection
bits : 25 - 28 (4 bit)
stream x number of data register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)
high interrupt flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEIF4 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 0 - 0 (1 bit)
CDMEIF4 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 2 - 2 (1 bit)
CTEIF4 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 3 - 3 (1 bit)
CHTIF4 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 4 - 4 (1 bit)
CTCIF4 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 5 - 5 (1 bit)
CFEIF5 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 6 - 6 (1 bit)
CDMEIF5 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 8 - 8 (1 bit)
CTEIF5 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 9 - 9 (1 bit)
CHTIF5 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 10 - 10 (1 bit)
CTCIF5 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 11 - 11 (1 bit)
CFEIF6 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 16 - 16 (1 bit)
CDMEIF6 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 18 - 18 (1 bit)
CTEIF6 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 19 - 19 (1 bit)
CHTIF6 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 20 - 20 (1 bit)
CTCIF6 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 21 - 21 (1 bit)
CFEIF7 : Stream x clear FIFO error interrupt flag (x = 7..4)
bits : 22 - 22 (1 bit)
CDMEIF7 : Stream x clear direct mode error interrupt flag (x = 7..4)
bits : 24 - 24 (1 bit)
CTEIF7 : Stream x clear transfer error interrupt flag (x = 7..4)
bits : 25 - 25 (1 bit)
CHTIF7 : Stream x clear half transfer interrupt flag (x = 7..4)
bits : 26 - 26 (1 bit)
CTCIF7 : Stream x clear transfer complete interrupt flag (x = 7..4)
bits : 27 - 27 (1 bit)
stream x peripheral address register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
stream x memory 0 address register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0A : Memory 0 address
bits : 0 - 31 (32 bit)
stream x memory 1 address register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1A : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)
stream x FIFO control register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold selection
bits : 0 - 1 (2 bit)
access : read-write
DMDIS : Direct mode disable
bits : 2 - 2 (1 bit)
access : read-write
FS : FIFO status
bits : 3 - 5 (3 bit)
access : read-only
FEIE : FIFO error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
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