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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR

CPAR1

CMAR1

CCR2

CNDTR2

CPAR2

CMAR2

CCR3

CNDTR3

CPAR3

CMAR3

IFCR

CCR4

CNDTR4

CPAR4

CMAR4

CCR5

CNDTR5

CPAR5

CMAR5

CCR6

CNDTR6

CPAR6

CMAR6

CCR1

CCR7

CNDTR7

CPAR7

CMAR7

CNDTR1


ISR

DMA interrupt status register (DMA_ISR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7

GIF1 : Channel 1 Global interrupt flag
bits : 0 - 0 (1 bit)

TCIF1 : Channel 1 Transfer Complete flag
bits : 1 - 1 (1 bit)

HTIF1 : Channel 1 Half Transfer Complete flag
bits : 2 - 2 (1 bit)

TEIF1 : Channel 1 Transfer Error flag
bits : 3 - 3 (1 bit)

GIF2 : Channel 2 Global interrupt flag
bits : 4 - 4 (1 bit)

TCIF2 : Channel 2 Transfer Complete flag
bits : 5 - 5 (1 bit)

HTIF2 : Channel 2 Half Transfer Complete flag
bits : 6 - 6 (1 bit)

TEIF2 : Channel 2 Transfer Error flag
bits : 7 - 7 (1 bit)

GIF3 : Channel 3 Global interrupt flag
bits : 8 - 8 (1 bit)

TCIF3 : Channel 3 Transfer Complete flag
bits : 9 - 9 (1 bit)

HTIF3 : Channel 3 Half Transfer Complete flag
bits : 10 - 10 (1 bit)

TEIF3 : Channel 3 Transfer Error flag
bits : 11 - 11 (1 bit)

GIF4 : Channel 4 Global interrupt flag
bits : 12 - 12 (1 bit)

TCIF4 : Channel 4 Transfer Complete flag
bits : 13 - 13 (1 bit)

HTIF4 : Channel 4 Half Transfer Complete flag
bits : 14 - 14 (1 bit)

TEIF4 : Channel 4 Transfer Error flag
bits : 15 - 15 (1 bit)

GIF5 : Channel 5 Global interrupt flag
bits : 16 - 16 (1 bit)

TCIF5 : Channel 5 Transfer Complete flag
bits : 17 - 17 (1 bit)

HTIF5 : Channel 5 Half Transfer Complete flag
bits : 18 - 18 (1 bit)

TEIF5 : Channel 5 Transfer Error flag
bits : 19 - 19 (1 bit)

GIF6 : Channel 6 Global interrupt flag
bits : 20 - 20 (1 bit)

TCIF6 : Channel 6 Transfer Complete flag
bits : 21 - 21 (1 bit)

HTIF6 : Channel 6 Half Transfer Complete flag
bits : 22 - 22 (1 bit)

TEIF6 : Channel 6 Transfer Error flag
bits : 23 - 23 (1 bit)

GIF7 : Channel 7 Global interrupt flag
bits : 24 - 24 (1 bit)

TCIF7 : Channel 7 Transfer Complete flag
bits : 25 - 25 (1 bit)

HTIF7 : Channel 7 Half Transfer Complete flag
bits : 26 - 26 (1 bit)

TEIF7 : Channel 7 Transfer Error flag
bits : 27 - 27 (1 bit)


CPAR1

DMA channel 1 peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR1 CPAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR1

DMA channel 1 memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR1 CMAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CCR2

DMA channel configuration register (DMA_CCR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNDTR2

DMA channel 2 number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR2 CNDTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


CPAR2

DMA channel 2 peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR2 CPAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR2

DMA channel 2 memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR2 CMAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CCR3

DMA channel configuration register (DMA_CCR)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR3 CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNDTR3

DMA channel 3 number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR3 CNDTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


CPAR3

DMA channel 3 peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR3 CPAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR3

DMA channel 3 memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR3 CMAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


IFCR

DMA interrupt flag clear register (DMA_IFCR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGIF1 CTCIF1 CHTIF1 CTEIF1 CGIF2 CTCIF2 CHTIF2 CTEIF2 CGIF3 CTCIF3 CHTIF3 CTEIF3 CGIF4 CTCIF4 CHTIF4 CTEIF4 CGIF5 CTCIF5 CHTIF5 CTEIF5 CGIF6 CTCIF6 CHTIF6 CTEIF6 CGIF7 CTCIF7 CHTIF7 CTEIF7

CGIF1 : Channel 1 Global interrupt clear
bits : 0 - 0 (1 bit)

CTCIF1 : Channel 1 Transfer Complete clear
bits : 1 - 1 (1 bit)

CHTIF1 : Channel 1 Half Transfer clear
bits : 2 - 2 (1 bit)

CTEIF1 : Channel 1 Transfer Error clear
bits : 3 - 3 (1 bit)

CGIF2 : Channel 2 Global interrupt clear
bits : 4 - 4 (1 bit)

CTCIF2 : Channel 2 Transfer Complete clear
bits : 5 - 5 (1 bit)

CHTIF2 : Channel 2 Half Transfer clear
bits : 6 - 6 (1 bit)

CTEIF2 : Channel 2 Transfer Error clear
bits : 7 - 7 (1 bit)

CGIF3 : Channel 3 Global interrupt clear
bits : 8 - 8 (1 bit)

CTCIF3 : Channel 3 Transfer Complete clear
bits : 9 - 9 (1 bit)

CHTIF3 : Channel 3 Half Transfer clear
bits : 10 - 10 (1 bit)

CTEIF3 : Channel 3 Transfer Error clear
bits : 11 - 11 (1 bit)

CGIF4 : Channel 4 Global interrupt clear
bits : 12 - 12 (1 bit)

CTCIF4 : Channel 4 Transfer Complete clear
bits : 13 - 13 (1 bit)

CHTIF4 : Channel 4 Half Transfer clear
bits : 14 - 14 (1 bit)

CTEIF4 : Channel 4 Transfer Error clear
bits : 15 - 15 (1 bit)

CGIF5 : Channel 5 Global interrupt clear
bits : 16 - 16 (1 bit)

CTCIF5 : Channel 5 Transfer Complete clear
bits : 17 - 17 (1 bit)

CHTIF5 : Channel 5 Half Transfer clear
bits : 18 - 18 (1 bit)

CTEIF5 : Channel 5 Transfer Error clear
bits : 19 - 19 (1 bit)

CGIF6 : Channel 6 Global interrupt clear
bits : 20 - 20 (1 bit)

CTCIF6 : Channel 6 Transfer Complete clear
bits : 21 - 21 (1 bit)

CHTIF6 : Channel 6 Half Transfer clear
bits : 22 - 22 (1 bit)

CTEIF6 : Channel 6 Transfer Error clear
bits : 23 - 23 (1 bit)

CGIF7 : Channel 7 Global interrupt clear
bits : 24 - 24 (1 bit)

CTCIF7 : Channel 7 Transfer Complete clear
bits : 25 - 25 (1 bit)

CHTIF7 : Channel 7 Half Transfer clear
bits : 26 - 26 (1 bit)

CTEIF7 : Channel 7 Transfer Error clear
bits : 27 - 27 (1 bit)


CCR4

DMA channel configuration register (DMA_CCR)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNDTR4

DMA channel 4 number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR4 CNDTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


CPAR4

DMA channel 4 peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR4 CPAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR4

DMA channel 4 memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR4 CMAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CCR5

DMA channel configuration register (DMA_CCR)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR5 CCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNDTR5

DMA channel 5 number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR5 CNDTR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


CPAR5

DMA channel 5 peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR5 CPAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR5

DMA channel 5 memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR5 CMAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CCR6

DMA channel configuration register (DMA_CCR)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR6 CCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNDTR6

DMA channel 6 number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR6 CNDTR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


CPAR6

DMA channel 6 peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR6 CPAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR6

DMA channel 6 memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR6 CMAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CCR1

DMA channel configuration register (DMA_CCR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CCR7

DMA channel configuration register (DMA_CCR)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR7 CCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNDTR7

DMA channel 7 number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR7 CNDTR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


CPAR7

DMA channel 7 peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR7 CPAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR7

DMA channel 7 memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR7 CMAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CNDTR1

DMA channel 1 number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR1 CNDTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)



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