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TIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

SR

EGR

CCMR1_Output

CCMR1_Input

CCER

CNT

PSC

ARR

RCR

CCR1

CCR2

CR2

BDTR

DCR

DMAR

SMCR

DIER


CR1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM ARPE CKD

CEN : Counter enable
bits : 0 - 0 (1 bit)

UDIS : Update disable
bits : 1 - 1 (1 bit)

URS : Update request source
bits : 2 - 2 (1 bit)

OPM : One-pulse mode
bits : 3 - 3 (1 bit)

ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)

CKD : Clock division
bits : 8 - 9 (2 bit)


SR

status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF COMIF TIF BIF CC1OF CC2OF

UIF : Update interrupt flag
bits : 0 - 0 (1 bit)

CC1IF : Capture/compare 1 interrupt flag
bits : 1 - 1 (1 bit)

CC2IF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)

COMIF : COM interrupt flag
bits : 5 - 5 (1 bit)

TIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)

BIF : Break interrupt flag
bits : 7 - 7 (1 bit)

CC1OF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)

CC2OF : Capture/compare 2 overcapture flag
bits : 10 - 10 (1 bit)


EGR

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EGR EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G COMG TG BG

UG : Update generation
bits : 0 - 0 (1 bit)

CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)

CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)

COMG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)

TG : Trigger generation
bits : 6 - 6 (1 bit)

BG : Break generation
bits : 7 - 7 (1 bit)


CCMR1_Output

capture/compare mode register (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMR1_Output CCMR1_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M CC2S OC2FE OC2PE OC2M

CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

OC1FE : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)

OC1PE : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)

OC1M : Output Compare 1 mode
bits : 4 - 6 (3 bit)

CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)

OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)

OC2M : Output Compare 2 mode
bits : 12 - 14 (3 bit)


CCMR1_Input

capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCMR1_Output
reset_Mask : 0x0

CCMR1_Input CCMR1_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S IC1PSC IC1F CC2S IC2PSC IC2F

CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

IC1PSC : Input capture 1 prescaler
bits : 2 - 3 (2 bit)

IC1F : Input capture 1 filter
bits : 4 - 7 (4 bit)

CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

IC2PSC : Input capture 2 prescaler
bits : 10 - 11 (2 bit)

IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)


CCER

capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCER CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NE CC1NP CC2E CC2P CC2NP

CC1E : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)

CC1P : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)

CC1NE : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)

CC1NP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)

CC2E : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)

CC2P : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)

CC2NP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)


CNT

counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : counter value
bits : 0 - 15 (16 bit)


PSC

prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : Prescaler value
bits : 0 - 15 (16 bit)


ARR

auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : Auto-reload value
bits : 0 - 15 (16 bit)


RCR

repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP

REP : Repetition counter value
bits : 0 - 7 (8 bit)


CCR1

capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : Capture/Compare 1 value
bits : 0 - 15 (16 bit)


CCR2

capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : Capture/Compare 2 value
bits : 0 - 15 (16 bit)


CR2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCPC CCUS CCDS MMS OIS1 OIS1N OIS2

CCPC : Capture/compare preloaded control
bits : 0 - 0 (1 bit)

CCUS : Capture/compare control update selection
bits : 2 - 2 (1 bit)

CCDS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)

MMS : Master mode selection
bits : 4 - 6 (3 bit)

OIS1 : Output Idle state 1
bits : 8 - 8 (1 bit)

OIS1N : Output Idle state 1
bits : 9 - 9 (1 bit)

OIS2 : Output Idle state 2
bits : 10 - 10 (1 bit)


BDTR

break and dead-time register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTR BDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTG LOCK OSSI OSSR BKE BKP AOE MOE

DTG : Dead-time generator setup
bits : 0 - 7 (8 bit)

LOCK : Lock configuration
bits : 8 - 9 (2 bit)

OSSI : Off-state selection for Idle mode
bits : 10 - 10 (1 bit)

OSSR : Off-state selection for Run mode
bits : 11 - 11 (1 bit)

BKE : Break enable
bits : 12 - 12 (1 bit)

BKP : Break polarity
bits : 13 - 13 (1 bit)

AOE : Automatic output enable
bits : 14 - 14 (1 bit)

MOE : Main output enable
bits : 15 - 15 (1 bit)


DCR

DMA control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA DBL

DBA : DMA base address
bits : 0 - 4 (5 bit)

DBL : DMA burst length
bits : 8 - 12 (5 bit)


DMAR

DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAR DMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAB

DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)


SMCR

slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCR SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM

SMS : Slave mode selection
bits : 0 - 2 (3 bit)

TS : Trigger selection
bits : 4 - 6 (3 bit)

MSM : Master/Slave mode
bits : 7 - 7 (1 bit)


DIER

DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIER DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE COMIE TIE BIE UDE CC1DE CC2DE TDE

UIE : Update interrupt enable
bits : 0 - 0 (1 bit)

CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)

CC2IE : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)

COMIE : COM interrupt enable
bits : 5 - 5 (1 bit)

TIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)

BIE : Break interrupt enable
bits : 7 - 7 (1 bit)

UDE : Update DMA request enable
bits : 8 - 8 (1 bit)

CC1DE : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)

CC2DE : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)

TDE : Trigger DMA request enable
bits : 14 - 14 (1 bit)



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