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TSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IOHCR

IOASCR

IOSCR

IOCCR

IOGCSR

IOG1CR

IOG2CR

IOG3CR

IER

IOG4CR

IOG5CR

IOG6CR

ICR

ISR


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSCE START AM SYNCPOL IODEF MCV PGPSC SSPSC SSE SSD CTPL CTPH

TSCE : Touch sensing controller enable
bits : 0 - 0 (1 bit)

START : Start a new acquisition
bits : 1 - 1 (1 bit)

AM : Acquisition mode
bits : 2 - 2 (1 bit)

SYNCPOL : Synchronization pin polarity
bits : 3 - 3 (1 bit)

IODEF : I/O Default mode
bits : 4 - 4 (1 bit)

MCV : Max count value
bits : 5 - 7 (3 bit)

PGPSC : pulse generator prescaler
bits : 12 - 14 (3 bit)

SSPSC : Spread spectrum prescaler
bits : 15 - 15 (1 bit)

SSE : Spread spectrum enable
bits : 16 - 16 (1 bit)

SSD : Spread spectrum deviation
bits : 17 - 23 (7 bit)

CTPL : Charge transfer pulse low
bits : 24 - 27 (4 bit)

CTPH : Charge transfer pulse high
bits : 28 - 31 (4 bit)


IOHCR

I/O hysteresis control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOHCR IOHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G1_IO1 G1_IO2 G1_IO3 G1_IO4 G2_IO1 G2_IO2 G2_IO3 G2_IO4 G3_IO1 G3_IO2 G3_IO3 G3_IO4 G4_IO1 G4_IO2 G4_IO3 G4_IO4 G5_IO1 G5_IO2 G5_IO3 G5_IO4 G6_IO1 G6_IO2 G6_IO3 G6_IO4

G1_IO1 : G1_IO1 Schmitt trigger hysteresis mode
bits : 0 - 0 (1 bit)

G1_IO2 : G1_IO2 Schmitt trigger hysteresis mode
bits : 1 - 1 (1 bit)

G1_IO3 : G1_IO3 Schmitt trigger hysteresis mode
bits : 2 - 2 (1 bit)

G1_IO4 : G1_IO4 Schmitt trigger hysteresis mode
bits : 3 - 3 (1 bit)

G2_IO1 : G2_IO1 Schmitt trigger hysteresis mode
bits : 4 - 4 (1 bit)

G2_IO2 : G2_IO2 Schmitt trigger hysteresis mode
bits : 5 - 5 (1 bit)

G2_IO3 : G2_IO3 Schmitt trigger hysteresis mode
bits : 6 - 6 (1 bit)

G2_IO4 : G2_IO4 Schmitt trigger hysteresis mode
bits : 7 - 7 (1 bit)

G3_IO1 : G3_IO1 Schmitt trigger hysteresis mode
bits : 8 - 8 (1 bit)

G3_IO2 : G3_IO2 Schmitt trigger hysteresis mode
bits : 9 - 9 (1 bit)

G3_IO3 : G3_IO3 Schmitt trigger hysteresis mode
bits : 10 - 10 (1 bit)

G3_IO4 : G3_IO4 Schmitt trigger hysteresis mode
bits : 11 - 11 (1 bit)

G4_IO1 : G4_IO1 Schmitt trigger hysteresis mode
bits : 12 - 12 (1 bit)

G4_IO2 : G4_IO2 Schmitt trigger hysteresis mode
bits : 13 - 13 (1 bit)

G4_IO3 : G4_IO3 Schmitt trigger hysteresis mode
bits : 14 - 14 (1 bit)

G4_IO4 : G4_IO4 Schmitt trigger hysteresis mode
bits : 15 - 15 (1 bit)

G5_IO1 : G5_IO1 Schmitt trigger hysteresis mode
bits : 16 - 16 (1 bit)

G5_IO2 : G5_IO2 Schmitt trigger hysteresis mode
bits : 17 - 17 (1 bit)

G5_IO3 : G5_IO3 Schmitt trigger hysteresis mode
bits : 18 - 18 (1 bit)

G5_IO4 : G5_IO4 Schmitt trigger hysteresis mode
bits : 19 - 19 (1 bit)

G6_IO1 : G6_IO1 Schmitt trigger hysteresis mode
bits : 20 - 20 (1 bit)

G6_IO2 : G6_IO2 Schmitt trigger hysteresis mode
bits : 21 - 21 (1 bit)

G6_IO3 : G6_IO3 Schmitt trigger hysteresis mode
bits : 22 - 22 (1 bit)

G6_IO4 : G6_IO4 Schmitt trigger hysteresis mode
bits : 23 - 23 (1 bit)


IOASCR

I/O analog switch control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOASCR IOASCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G1_IO1 G1_IO2 G1_IO3 G1_IO4 G2_IO1 G2_IO2 G2_IO3 G2_IO4 G3_IO1 G3_IO2 G3_IO3 G3_IO4 G4_IO1 G4_IO2 G4_IO3 G4_IO4 G5_IO1 G5_IO2 G5_IO3 G5_IO4 G6_IO1 G6_IO2 G6_IO3 G6_IO4

G1_IO1 : G1_IO1 analog switch enable
bits : 0 - 0 (1 bit)

G1_IO2 : G1_IO2 analog switch enable
bits : 1 - 1 (1 bit)

G1_IO3 : G1_IO3 analog switch enable
bits : 2 - 2 (1 bit)

G1_IO4 : G1_IO4 analog switch enable
bits : 3 - 3 (1 bit)

G2_IO1 : G2_IO1 analog switch enable
bits : 4 - 4 (1 bit)

G2_IO2 : G2_IO2 analog switch enable
bits : 5 - 5 (1 bit)

G2_IO3 : G2_IO3 analog switch enable
bits : 6 - 6 (1 bit)

G2_IO4 : G2_IO4 analog switch enable
bits : 7 - 7 (1 bit)

G3_IO1 : G3_IO1 analog switch enable
bits : 8 - 8 (1 bit)

G3_IO2 : G3_IO2 analog switch enable
bits : 9 - 9 (1 bit)

G3_IO3 : G3_IO3 analog switch enable
bits : 10 - 10 (1 bit)

G3_IO4 : G3_IO4 analog switch enable
bits : 11 - 11 (1 bit)

G4_IO1 : G4_IO1 analog switch enable
bits : 12 - 12 (1 bit)

G4_IO2 : G4_IO2 analog switch enable
bits : 13 - 13 (1 bit)

G4_IO3 : G4_IO3 analog switch enable
bits : 14 - 14 (1 bit)

G4_IO4 : G4_IO4 analog switch enable
bits : 15 - 15 (1 bit)

G5_IO1 : G5_IO1 analog switch enable
bits : 16 - 16 (1 bit)

G5_IO2 : G5_IO2 analog switch enable
bits : 17 - 17 (1 bit)

G5_IO3 : G5_IO3 analog switch enable
bits : 18 - 18 (1 bit)

G5_IO4 : G5_IO4 analog switch enable
bits : 19 - 19 (1 bit)

G6_IO1 : G6_IO1 analog switch enable
bits : 20 - 20 (1 bit)

G6_IO2 : G6_IO2 analog switch enable
bits : 21 - 21 (1 bit)

G6_IO3 : G6_IO3 analog switch enable
bits : 22 - 22 (1 bit)

G6_IO4 : G6_IO4 analog switch enable
bits : 23 - 23 (1 bit)


IOSCR

I/O sampling control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOSCR IOSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G1_IO1 G1_IO2 G1_IO3 G1_IO4 G2_IO1 G2_IO2 G2_IO3 G2_IO4 G3_IO1 G3_IO2 G3_IO3 G3_IO4 G4_IO1 G4_IO2 G4_IO3 G4_IO4 G5_IO1 G5_IO2 G5_IO3 G5_IO4 G6_IO1 G6_IO2 G6_IO3 G6_IO4

G1_IO1 : G1_IO1 sampling mode
bits : 0 - 0 (1 bit)

G1_IO2 : G1_IO2 sampling mode
bits : 1 - 1 (1 bit)

G1_IO3 : G1_IO3 sampling mode
bits : 2 - 2 (1 bit)

G1_IO4 : G1_IO4 sampling mode
bits : 3 - 3 (1 bit)

G2_IO1 : G2_IO1 sampling mode
bits : 4 - 4 (1 bit)

G2_IO2 : G2_IO2 sampling mode
bits : 5 - 5 (1 bit)

G2_IO3 : G2_IO3 sampling mode
bits : 6 - 6 (1 bit)

G2_IO4 : G2_IO4 sampling mode
bits : 7 - 7 (1 bit)

G3_IO1 : G3_IO1 sampling mode
bits : 8 - 8 (1 bit)

G3_IO2 : G3_IO2 sampling mode
bits : 9 - 9 (1 bit)

G3_IO3 : G3_IO3 sampling mode
bits : 10 - 10 (1 bit)

G3_IO4 : G3_IO4 sampling mode
bits : 11 - 11 (1 bit)

G4_IO1 : G4_IO1 sampling mode
bits : 12 - 12 (1 bit)

G4_IO2 : G4_IO2 sampling mode
bits : 13 - 13 (1 bit)

G4_IO3 : G4_IO3 sampling mode
bits : 14 - 14 (1 bit)

G4_IO4 : G4_IO4 sampling mode
bits : 15 - 15 (1 bit)

G5_IO1 : G5_IO1 sampling mode
bits : 16 - 16 (1 bit)

G5_IO2 : G5_IO2 sampling mode
bits : 17 - 17 (1 bit)

G5_IO3 : G5_IO3 sampling mode
bits : 18 - 18 (1 bit)

G5_IO4 : G5_IO4 sampling mode
bits : 19 - 19 (1 bit)

G6_IO1 : G6_IO1 sampling mode
bits : 20 - 20 (1 bit)

G6_IO2 : G6_IO2 sampling mode
bits : 21 - 21 (1 bit)

G6_IO3 : G6_IO3 sampling mode
bits : 22 - 22 (1 bit)

G6_IO4 : G6_IO4 sampling mode
bits : 23 - 23 (1 bit)


IOCCR

I/O channel control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCCR IOCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G1_IO1 G1_IO2 G1_IO3 G1_IO4 G2_IO1 G2_IO2 G2_IO3 G2_IO4 G3_IO1 G3_IO2 G3_IO3 G3_IO4 G4_IO1 G4_IO2 G4_IO3 G4_IO4 G5_IO1 G5_IO2 G5_IO3 G5_IO4 G6_IO1 G6_IO2 G6_IO3 G6_IO4

G1_IO1 : G1_IO1 channel mode
bits : 0 - 0 (1 bit)

G1_IO2 : G1_IO2 channel mode
bits : 1 - 1 (1 bit)

G1_IO3 : G1_IO3 channel mode
bits : 2 - 2 (1 bit)

G1_IO4 : G1_IO4 channel mode
bits : 3 - 3 (1 bit)

G2_IO1 : G2_IO1 channel mode
bits : 4 - 4 (1 bit)

G2_IO2 : G2_IO2 channel mode
bits : 5 - 5 (1 bit)

G2_IO3 : G2_IO3 channel mode
bits : 6 - 6 (1 bit)

G2_IO4 : G2_IO4 channel mode
bits : 7 - 7 (1 bit)

G3_IO1 : G3_IO1 channel mode
bits : 8 - 8 (1 bit)

G3_IO2 : G3_IO2 channel mode
bits : 9 - 9 (1 bit)

G3_IO3 : G3_IO3 channel mode
bits : 10 - 10 (1 bit)

G3_IO4 : G3_IO4 channel mode
bits : 11 - 11 (1 bit)

G4_IO1 : G4_IO1 channel mode
bits : 12 - 12 (1 bit)

G4_IO2 : G4_IO2 channel mode
bits : 13 - 13 (1 bit)

G4_IO3 : G4_IO3 channel mode
bits : 14 - 14 (1 bit)

G4_IO4 : G4_IO4 channel mode
bits : 15 - 15 (1 bit)

G5_IO1 : G5_IO1 channel mode
bits : 16 - 16 (1 bit)

G5_IO2 : G5_IO2 channel mode
bits : 17 - 17 (1 bit)

G5_IO3 : G5_IO3 channel mode
bits : 18 - 18 (1 bit)

G5_IO4 : G5_IO4 channel mode
bits : 19 - 19 (1 bit)

G6_IO1 : G6_IO1 channel mode
bits : 20 - 20 (1 bit)

G6_IO2 : G6_IO2 channel mode
bits : 21 - 21 (1 bit)

G6_IO3 : G6_IO3 channel mode
bits : 22 - 22 (1 bit)

G6_IO4 : G6_IO4 channel mode
bits : 23 - 23 (1 bit)


IOGCSR

I/O group control status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOGCSR IOGCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G1E G2E G3E G4E G5E G6E G7E G8E G1S G2S G3S G4S G5S G6S G7S G8S

G1E : Analog I/O group x enable
bits : 0 - 0 (1 bit)
access : read-write

G2E : Analog I/O group x enable
bits : 1 - 1 (1 bit)
access : read-write

G3E : Analog I/O group x enable
bits : 2 - 2 (1 bit)
access : read-write

G4E : Analog I/O group x enable
bits : 3 - 3 (1 bit)
access : read-write

G5E : Analog I/O group x enable
bits : 4 - 4 (1 bit)
access : read-write

G6E : Analog I/O group x enable
bits : 5 - 5 (1 bit)
access : read-write

G7E : Analog I/O group x enable
bits : 6 - 6 (1 bit)
access : read-write

G8E : Analog I/O group x enable
bits : 7 - 7 (1 bit)
access : read-write

G1S : Analog I/O group x status
bits : 16 - 16 (1 bit)
access : read-only

G2S : Analog I/O group x status
bits : 17 - 17 (1 bit)
access : read-only

G3S : Analog I/O group x status
bits : 18 - 18 (1 bit)
access : read-only

G4S : Analog I/O group x status
bits : 19 - 19 (1 bit)
access : read-only

G5S : Analog I/O group x status
bits : 20 - 20 (1 bit)
access : read-only

G6S : Analog I/O group x status
bits : 21 - 21 (1 bit)
access : read-only

G7S : Analog I/O group x status
bits : 22 - 22 (1 bit)
access : read-write

G8S : Analog I/O group x status
bits : 23 - 23 (1 bit)
access : read-write


IOG1CR

I/O group x counter register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOG1CR IOG1CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 13 (14 bit)


IOG2CR

I/O group x counter register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOG2CR IOG2CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 13 (14 bit)


IOG3CR

I/O group x counter register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOG3CR IOG3CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 13 (14 bit)


IER

interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOAIE MCEIE

EOAIE : End of acquisition interrupt enable
bits : 0 - 0 (1 bit)

MCEIE : Max count error interrupt enable
bits : 1 - 1 (1 bit)


IOG4CR

I/O group x counter register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOG4CR IOG4CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 13 (14 bit)


IOG5CR

I/O group x counter register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOG5CR IOG5CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 13 (14 bit)


IOG6CR

I/O group x counter register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOG6CR IOG6CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 13 (14 bit)


ICR

interrupt clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOAIC MCEIC

EOAIC : End of acquisition interrupt clear
bits : 0 - 0 (1 bit)

MCEIC : Max count error interrupt clear
bits : 1 - 1 (1 bit)


ISR

interrupt status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOAF MCEF

EOAF : End of acquisition flag
bits : 0 - 0 (1 bit)

MCEF : Max count error flag
bits : 1 - 1 (1 bit)



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