\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
DBGMCU_IDCODE
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device identifier
bits : 0 - 11 (12 bit)
REV_ID : Revision identifie
bits : 16 - 31 (16 bit)
Debug MCU configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_STOP : Debug Stop mode
bits : 1 - 1 (1 bit)
DBG_STANDBY : Debug Standby mode
bits : 2 - 2 (1 bit)
Debug MCU APB1 freeze register1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM2_STOP : TIM2 counter stopped when core is halted
bits : 0 - 0 (1 bit)
DBG_TIM3_STOP : TIM3 counter stopped when core is halted
bits : 1 - 1 (1 bit)
DBG_RTC_STOP : RTC counter stopped when core is halted
bits : 10 - 10 (1 bit)
DBG_WWDG_STOP : Window watchdog counter stopped when core is halted
bits : 11 - 11 (1 bit)
DBG_IWDG_STOP : Independent watchdog counter stopped when core is halted
bits : 12 - 12 (1 bit)
DBG_I2C1_STOP : I2C1 SMBUS timeout counter stopped when core is halted
bits : 21 - 21 (1 bit)
Debug MCU APB1 freeze register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 11 - 11 (1 bit)
DBG_TIM14_STOP : DBG_TIM14_STOP
bits : 15 - 15 (1 bit)
DBG_TIM16_STOP : DBG_TIM16_STOP
bits : 17 - 17 (1 bit)
DBG_TIM17_STOP : DBG_TIM17_STOP
bits : 18 - 18 (1 bit)
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