\n

TAMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

BKP0R

BKP1R

BKP2R

BKP3R

BKP4R

IER

SR

MISR

SCR

CR2

FLTCR


CR1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1E TAMP2E ITAMP1E ITAMP3E ITAMP4E ITAMP5E ITAMP6E

TAMP1E : TAMP1E
bits : 0 - 0 (1 bit)

TAMP2E : TAMP2E
bits : 1 - 1 (1 bit)

ITAMP1E : ITAMP1E
bits : 16 - 16 (1 bit)

ITAMP3E : ITAMP3E
bits : 18 - 18 (1 bit)

ITAMP4E : ITAMP4E
bits : 19 - 19 (1 bit)

ITAMP5E : ITAMP5E
bits : 20 - 20 (1 bit)

ITAMP6E : ITAMP6E
bits : 21 - 21 (1 bit)


BKP0R

TAMP backup register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP0R BKP0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP1R

TAMP backup register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP1R BKP1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP2R

TAMP backup register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP2R BKP2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP3R

TAMP backup register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP3R BKP3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP4R

TAMP backup register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP4R BKP4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


IER

TAMP interrupt enable register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1IE TAMP2IE ITAMP1IE ITAMP3IE ITAMP4IE ITAMP5IE ITAMP6IE

TAMP1IE : TAMP1IE
bits : 0 - 0 (1 bit)

TAMP2IE : TAMP2IE
bits : 1 - 1 (1 bit)

ITAMP1IE : ITAMP1IE
bits : 16 - 16 (1 bit)

ITAMP3IE : ITAMP3IE
bits : 18 - 18 (1 bit)

ITAMP4IE : ITAMP4IE
bits : 19 - 19 (1 bit)

ITAMP5IE : ITAMP5IE
bits : 20 - 20 (1 bit)

ITAMP6IE : ITAMP6IE
bits : 21 - 21 (1 bit)


SR

TAMP status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1F TAMP2F ITAMP1F ITAMP3F ITAMP4F ITAMP5F ITAMP6F ITAMP7F

TAMP1F : TAMP1F
bits : 0 - 0 (1 bit)

TAMP2F : TAMP2F
bits : 1 - 1 (1 bit)

ITAMP1F : ITAMP1F
bits : 16 - 16 (1 bit)

ITAMP3F : ITAMP3F
bits : 18 - 18 (1 bit)

ITAMP4F : ITAMP4F
bits : 19 - 19 (1 bit)

ITAMP5F : ITAMP5F
bits : 20 - 20 (1 bit)

ITAMP6F : ITAMP6F
bits : 21 - 21 (1 bit)

ITAMP7F : ITAMP7F
bits : 22 - 22 (1 bit)


MISR

TAMP masked interrupt status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MISR MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1MF TAMP2MF ITAMP1MF ITAMP3MF ITAMP4MF ITAMP5MF ITAMP6MF

TAMP1MF : TAMP1MF:
bits : 0 - 0 (1 bit)

TAMP2MF : TAMP2MF
bits : 1 - 1 (1 bit)

ITAMP1MF : ITAMP1MF
bits : 16 - 16 (1 bit)

ITAMP3MF : ITAMP3MF
bits : 18 - 18 (1 bit)

ITAMP4MF : ITAMP4MF
bits : 19 - 19 (1 bit)

ITAMP5MF : ITAMP5MF
bits : 20 - 20 (1 bit)

ITAMP6MF : ITAMP6MF
bits : 21 - 21 (1 bit)


SCR

TAMP status clear register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTAMP1F CTAMP2F CITAMP1F CITAMP3F CITAMP4F CITAMP5F CITAMP6F CITAMP7F

CTAMP1F : CTAMP1F
bits : 0 - 0 (1 bit)

CTAMP2F : CTAMP2F
bits : 1 - 1 (1 bit)

CITAMP1F : CITAMP1F
bits : 16 - 16 (1 bit)

CITAMP3F : CITAMP3F
bits : 18 - 18 (1 bit)

CITAMP4F : CITAMP4F
bits : 19 - 19 (1 bit)

CITAMP5F : CITAMP5F
bits : 20 - 20 (1 bit)

CITAMP6F : CITAMP6F
bits : 21 - 21 (1 bit)

CITAMP7F : CITAMP7F
bits : 22 - 22 (1 bit)


CR2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1NOER TAMP2NOER TAMP1MSK TAMP2MSK TAMP1TRG TAMP2TRG

TAMP1NOER : TAMP1NOER
bits : 0 - 0 (1 bit)

TAMP2NOER : TAMP2NOER
bits : 1 - 1 (1 bit)

TAMP1MSK : TAMP1MSK
bits : 16 - 16 (1 bit)

TAMP2MSK : TAMP2MSK
bits : 17 - 17 (1 bit)

TAMP1TRG : TAMP1TRG
bits : 24 - 24 (1 bit)

TAMP2TRG : TAMP2TRG
bits : 25 - 25 (1 bit)


FLTCR

TAMP filter control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLTCR FLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMPFREQ TAMPFLT TAMPPRCH TAMPPUDIS

TAMPFREQ : TAMPFREQ
bits : 0 - 2 (3 bit)

TAMPFLT : TAMPFLT
bits : 3 - 4 (2 bit)

TAMPPRCH : TAMPPRCH
bits : 5 - 6 (2 bit)

TAMPPUDIS : TAMPPUDIS
bits : 7 - 7 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.