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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EP0R

EP4R

EP5R

EP6R

EP7R

EP1R

CNTR

ISTR

FNR

DADDR

BTABLE

LPMCSR

BCDR

EP2R

EP3R


EP0R

endpoint 0 register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0R EP0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP4R

endpoint 4 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP4R EP4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP5R

endpoint 5 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP5R EP5R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP6R

endpoint 6 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP6R EP6R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP7R

endpoint 7 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP7R EP7R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP1R

endpoint 1 register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP1R EP1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


CNTR

control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRES PDWN LPMODE FSUSP RESUME L1RESUME L1REQM ESOFM SOFM RESETM SUSPM WKUPM ERRM PMAOVRM CTRM

FRES : Force USB Reset
bits : 0 - 0 (1 bit)

PDWN : Power down
bits : 1 - 1 (1 bit)

LPMODE : Low-power mode
bits : 2 - 2 (1 bit)

FSUSP : Force suspend
bits : 3 - 3 (1 bit)

RESUME : Resume request
bits : 4 - 4 (1 bit)

L1RESUME : LPM L1 Resume request
bits : 5 - 5 (1 bit)

L1REQM : LPM L1 state request interrupt mask
bits : 7 - 7 (1 bit)

ESOFM : Expected start of frame interrupt mask
bits : 8 - 8 (1 bit)

SOFM : Start of frame interrupt mask
bits : 9 - 9 (1 bit)

RESETM : USB reset interrupt mask
bits : 10 - 10 (1 bit)

SUSPM : Suspend mode interrupt mask
bits : 11 - 11 (1 bit)

WKUPM : Wakeup interrupt mask
bits : 12 - 12 (1 bit)

ERRM : Error interrupt mask
bits : 13 - 13 (1 bit)

PMAOVRM : Packet memory area over / underrun interrupt mask
bits : 14 - 14 (1 bit)

CTRM : Correct transfer interrupt mask
bits : 15 - 15 (1 bit)


ISTR

interrupt status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISTR ISTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ID DIR L1REQ ESOF SOF RESET SUSP WKUP ERR PMAOVR CTR

EP_ID : Endpoint Identifier
bits : 0 - 3 (4 bit)
access : read-only

DIR : Direction of transaction
bits : 4 - 4 (1 bit)
access : read-only

L1REQ : LPM L1 state request
bits : 7 - 7 (1 bit)
access : read-write

ESOF : Expected start frame
bits : 8 - 8 (1 bit)
access : read-write

SOF : start of frame
bits : 9 - 9 (1 bit)
access : read-write

RESET : reset request
bits : 10 - 10 (1 bit)
access : read-write

SUSP : Suspend mode request
bits : 11 - 11 (1 bit)
access : read-write

WKUP : Wakeup
bits : 12 - 12 (1 bit)
access : read-write

ERR : Error
bits : 13 - 13 (1 bit)
access : read-write

PMAOVR : Packet memory area over / underrun
bits : 14 - 14 (1 bit)
access : read-write

CTR : Correct transfer
bits : 15 - 15 (1 bit)
access : read-only


FNR

frame number register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FNR FNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FN LSOF LCK RXDM RXDP

FN : Frame number
bits : 0 - 10 (11 bit)

LSOF : Lost SOF
bits : 11 - 12 (2 bit)

LCK : Locked
bits : 13 - 13 (1 bit)

RXDM : Receive data - line status
bits : 14 - 14 (1 bit)

RXDP : Receive data + line status
bits : 15 - 15 (1 bit)


DADDR

device address
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADDR DADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD EF

ADD : Device address
bits : 0 - 6 (7 bit)

EF : Enable function
bits : 7 - 7 (1 bit)


BTABLE

Buffer table address
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTABLE BTABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTABLE

BTABLE : Buffer table
bits : 3 - 15 (13 bit)


LPMCSR

LPM control and status register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPMCSR LPMCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMEN LPMACK REMWAKE BESL

LPMEN : LPM support enable
bits : 0 - 0 (1 bit)
access : read-write

LPMACK : LPM Token acknowledge enable
bits : 1 - 1 (1 bit)
access : read-write

REMWAKE : bRemoteWake value
bits : 3 - 3 (1 bit)
access : read-only

BESL : BESL value
bits : 4 - 7 (4 bit)
access : read-only


BCDR

Battery charging detector
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCDR BCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCDEN DCDEN PDEN SDEN DCDET PDET SDET PS2DET DPPU

BCDEN : Battery charging detector (BCD) enable
bits : 0 - 0 (1 bit)
access : read-write

DCDEN : Data contact detection (DCD) mode enable
bits : 1 - 1 (1 bit)
access : read-write

PDEN : Primary detection (PD) mode enable
bits : 2 - 2 (1 bit)
access : read-write

SDEN : Secondary detection (SD) mode enable
bits : 3 - 3 (1 bit)
access : read-write

DCDET : Data contact detection (DCD) status
bits : 4 - 4 (1 bit)
access : read-only

PDET : Primary detection (PD) status
bits : 5 - 5 (1 bit)
access : read-only

SDET : Secondary detection (SD) status
bits : 6 - 6 (1 bit)
access : read-only

PS2DET : DM pull-up detection status
bits : 7 - 7 (1 bit)
access : read-only

DPPU : DP pull-up control
bits : 15 - 15 (1 bit)
access : read-write


EP2R

endpoint 2 register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP2R EP2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP3R

endpoint 3 register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP3R EP3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EP_TYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : Endpoint address
bits : 0 - 3 (4 bit)

STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)

EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)



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