\n
address_offset : 0x0 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection : not protected
interrupt line 0 status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WWDG : Window watchdog interrupt pending flag
bits : 0 - 0 (1 bit)
interrupt line 1 status register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PVDOUT : PVD supply monitoring interrupt request pending (EXTI line 16).
bits : 0 - 0 (1 bit)
interrupt line 2 status register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAMP : TAMP
bits : 0 - 0 (1 bit)
RTC : RTC
bits : 1 - 1 (1 bit)
interrupt line 3 status register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLASH_ITF : FLASH_ITF
bits : 0 - 0 (1 bit)
FLASH_ECC : FLASH_ECC
bits : 1 - 1 (1 bit)
interrupt line 4 status register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCC : RCC
bits : 0 - 0 (1 bit)
interrupt line 5 status register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTI0 : EXTI0
bits : 0 - 0 (1 bit)
EXTI1 : EXTI1
bits : 1 - 1 (1 bit)
interrupt line 6 status register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTI2 : EXTI2
bits : 0 - 0 (1 bit)
EXTI3 : EXTI3
bits : 1 - 1 (1 bit)
interrupt line 7 status register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTI4 : EXTI4
bits : 0 - 0 (1 bit)
EXTI5 : EXTI5
bits : 1 - 1 (1 bit)
EXTI6 : EXTI6
bits : 2 - 2 (1 bit)
EXTI7 : EXTI7
bits : 3 - 3 (1 bit)
EXTI8 : EXTI8
bits : 4 - 4 (1 bit)
EXTI9 : EXTI9
bits : 5 - 5 (1 bit)
EXTI10 : EXTI10
bits : 6 - 6 (1 bit)
EXTI11 : EXTI11
bits : 7 - 7 (1 bit)
EXTI12 : EXTI12
bits : 8 - 8 (1 bit)
EXTI13 : EXTI13
bits : 9 - 9 (1 bit)
EXTI14 : EXTI14
bits : 10 - 10 (1 bit)
EXTI15 : EXTI15
bits : 11 - 11 (1 bit)
interrupt line 9 status register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA1_CH1 : DMA1_CH1
bits : 0 - 0 (1 bit)
interrupt line 10 status register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA1_CH2 : DMA1_CH1
bits : 0 - 0 (1 bit)
DMA1_CH3 : DMA1_CH3
bits : 1 - 1 (1 bit)
interrupt line 11 status register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAMUX : DMAMUX
bits : 0 - 0 (1 bit)
DMA1_CH4 : DMA1_CH4
bits : 1 - 1 (1 bit)
DMA1_CH5 : DMA1_CH5
bits : 2 - 2 (1 bit)
interrupt line 12 status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC : ADC
bits : 0 - 0 (1 bit)
interrupt line 13 status register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM1_CCU : TIM1_CCU
bits : 0 - 0 (1 bit)
TIM1_TRG : TIM1_TRG
bits : 1 - 1 (1 bit)
TIM1_UPD : TIM1_UPD
bits : 2 - 2 (1 bit)
TIM1_BRK : TIM1_BRK
bits : 3 - 3 (1 bit)
interrupt line 14 status register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM1_CC : TIM1_CC
bits : 0 - 0 (1 bit)
interrupt line 15 status register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM2 : TIM2
bits : 0 - 0 (1 bit)
interrupt line 16 status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM3 : TIM3
bits : 0 - 0 (1 bit)
interrupt line 17 status register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPTIM1 : LPTIM1
bits : 2 - 2 (1 bit)
interrupt line 18 status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPTIM2 : LPTIM2
bits : 1 - 1 (1 bit)
interrupt line 19 status register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM14 : TIM14
bits : 0 - 0 (1 bit)
interrupt line 21 status register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM16 : TIM16
bits : 0 - 0 (1 bit)
interrupt line 22 status register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIM17 : TIM17
bits : 0 - 0 (1 bit)
interrupt line 23 status register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2C1 : I2C1
bits : 0 - 0 (1 bit)
interrupt line 24 status register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2C2 : I2C2
bits : 0 - 0 (1 bit)
interrupt line 25 status register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI1 : SPI1
bits : 0 - 0 (1 bit)
interrupt line 26 status register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI2 : SPI2
bits : 0 - 0 (1 bit)
interrupt line 27 status register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USART1 : USART1
bits : 0 - 0 (1 bit)
interrupt line 28 status register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USART2 : USART2
bits : 0 - 0 (1 bit)
interrupt line 29 status register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USART5 : USART5
bits : 2 - 2 (1 bit)
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