\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
low interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF0 : Channel global interrupt flag
bits : 0 - 0 (1 bit)
TCIF1 : Channel transfer complete flag
bits : 1 - 1 (1 bit)
HTIF2 : Channel half transfer flag
bits : 2 - 2 (1 bit)
TEIF3 : Channel transfer error flag
bits : 3 - 3 (1 bit)
GIF4 : Channel global interrupt flag
bits : 4 - 4 (1 bit)
TCIF5 : Channel transfer complete flag
bits : 5 - 5 (1 bit)
HTIF6 : Channel half transfer flag
bits : 6 - 6 (1 bit)
TEIF7 : Channel transfer error flag
bits : 7 - 7 (1 bit)
GIF8 : Channel global interrupt flag
bits : 8 - 8 (1 bit)
TCIF9 : Channel transfer complete flag
bits : 9 - 9 (1 bit)
HTIF10 : Channel half transfer flag
bits : 10 - 10 (1 bit)
TEIF11 : Channel transfer error flag
bits : 11 - 11 (1 bit)
GIF12 : Channel global interrupt flag
bits : 12 - 12 (1 bit)
TCIF13 : Channel transfer complete flag
bits : 13 - 13 (1 bit)
HTIF14 : Channel half transfer flag
bits : 14 - 14 (1 bit)
TEIF15 : Channel transfer error flag
bits : 15 - 15 (1 bit)
GIF16 : Channel global interrupt flag
bits : 16 - 16 (1 bit)
TCIF17 : Channel transfer complete flag
bits : 17 - 17 (1 bit)
HTIF18 : Channel half transfer flag
bits : 18 - 18 (1 bit)
TEIF19 : Channel transfer error flag
bits : 19 - 19 (1 bit)
GIF20 : Channel global interrupt flag
bits : 20 - 20 (1 bit)
TCIF21 : Channel transfer complete flag
bits : 21 - 21 (1 bit)
HTIF22 : Channel half transfer flag
bits : 22 - 22 (1 bit)
TEIF23 : Channel transfer error flag
bits : 23 - 23 (1 bit)
GIF24 : Channel global interrupt flag
bits : 24 - 24 (1 bit)
TCIF25 : Channel transfer complete flag
bits : 25 - 25 (1 bit)
HTIF26 : Channel half transfer flag
bits : 26 - 26 (1 bit)
TEIF27 : Channel transfer error flag
bits : 27 - 27 (1 bit)
DMA channel x peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel x memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
DMA channel x configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel x peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel x memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
DMA channel x configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel x configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel x peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel x memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
high interrupt status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CGIF0 : Channel global interrupt flag
bits : 0 - 0 (1 bit)
CTCIF1 : Channel transfer complete flag
bits : 1 - 1 (1 bit)
CHTIF2 : Channel half transfer flag
bits : 2 - 2 (1 bit)
CTEIF3 : Channel transfer error flag
bits : 3 - 3 (1 bit)
CGIF4 : Channel global interrupt flag
bits : 4 - 4 (1 bit)
CTCIF5 : Channel transfer complete flag
bits : 5 - 5 (1 bit)
CHTIF6 : Channel half transfer flag
bits : 6 - 6 (1 bit)
CTEIF7 : Channel transfer error flag
bits : 7 - 7 (1 bit)
CGIF8 : Channel global interrupt flag
bits : 8 - 8 (1 bit)
CTCIF9 : Channel transfer complete flag
bits : 9 - 9 (1 bit)
CHTIF10 : Channel half transfer flag
bits : 10 - 10 (1 bit)
CTEIF11 : Channel transfer error flag
bits : 11 - 11 (1 bit)
CGIF12 : Channel global interrupt flag
bits : 12 - 12 (1 bit)
CTCIF13 : Channel transfer complete flag
bits : 13 - 13 (1 bit)
CHTIF14 : Channel half transfer flag
bits : 14 - 14 (1 bit)
CTEIF15 : Channel transfer error flag
bits : 15 - 15 (1 bit)
CGIF16 : Channel global interrupt flag
bits : 16 - 16 (1 bit)
CTCIF17 : Channel transfer complete flag
bits : 17 - 17 (1 bit)
CHTIF18 : Channel half transfer flag
bits : 18 - 18 (1 bit)
CTEIF19 : Channel transfer error flag
bits : 19 - 19 (1 bit)
CGIF20 : Channel global interrupt flag
bits : 20 - 20 (1 bit)
CTCIF21 : Channel transfer complete flag
bits : 21 - 21 (1 bit)
CHTIF22 : Channel half transfer flag
bits : 22 - 22 (1 bit)
CTEIF23 : Channel transfer error flag
bits : 23 - 23 (1 bit)
CGIF24 : Channel global interrupt flag
bits : 24 - 24 (1 bit)
CTCIF25 : Channel transfer complete flag
bits : 25 - 25 (1 bit)
CHTIF26 : Channel half transfer flag
bits : 26 - 26 (1 bit)
CTEIF27 : Channel transfer error flag
bits : 27 - 27 (1 bit)
DMA channel x configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel x configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel x peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel x memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
DMA channel x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel x configuration register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel x memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
DMA channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
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