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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RTSR1

FPR1

FTSR1

EXTICR1

EXTICR2

EXTICR3

EXTICR4

SWIER1

IMR1

EMR1

RPR1


RTSR1

EXTI rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTSR1 RTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9 TR10 TR11 TR12 TR13 TR14 TR15 TR16

TR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)

TR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)

TR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)

TR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)

TR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)

TR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)

TR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)

TR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)

TR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)

TR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)

TR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)

TR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)

TR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)

TR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)

TR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)

TR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)

TR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)


FPR1

EXTI falling edge pending register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPR1 FPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPIF0 FPIF1 FPIF2 FPIF3 FPIF4 FPIF5 FPIF6 FPIF7 FPIF8 FPIF9 FPIF10 FPIF11 FPIF12 FPIF13 FPIF14 FPIF15 FPIF16

FPIF0 : configurable event inputs x falling edge pending bit.
bits : 0 - 0 (1 bit)

FPIF1 : configurable event inputs x falling edge pending bit.
bits : 1 - 1 (1 bit)

FPIF2 : configurable event inputs x falling edge pending bit.
bits : 2 - 2 (1 bit)

FPIF3 : configurable event inputs x falling edge pending bit.
bits : 3 - 3 (1 bit)

FPIF4 : configurable event inputs x falling edge pending bit.
bits : 4 - 4 (1 bit)

FPIF5 : configurable event inputs x falling edge pending bit.
bits : 5 - 5 (1 bit)

FPIF6 : configurable event inputs x falling edge pending bit.
bits : 6 - 6 (1 bit)

FPIF7 : configurable event inputs x falling edge pending bit.
bits : 7 - 7 (1 bit)

FPIF8 : configurable event inputs x falling edge pending bit.
bits : 8 - 8 (1 bit)

FPIF9 : configurable event inputs x falling edge pending bit.
bits : 9 - 9 (1 bit)

FPIF10 : configurable event inputs x falling edge pending bit.
bits : 10 - 10 (1 bit)

FPIF11 : configurable event inputs x falling edge pending bit.
bits : 11 - 11 (1 bit)

FPIF12 : configurable event inputs x falling edge pending bit.
bits : 12 - 12 (1 bit)

FPIF13 : configurable event inputs x falling edge pending bit.
bits : 13 - 13 (1 bit)

FPIF14 : configurable event inputs x falling edge pending bit.
bits : 14 - 14 (1 bit)

FPIF15 : configurable event inputs x falling edge pending bit.
bits : 15 - 15 (1 bit)

FPIF16 : configurable event inputs x falling edge pending bit.
bits : 16 - 16 (1 bit)


FTSR1

EXTI falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTSR1 FTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9 TR10 TR11 TR12 TR13 TR14 TR15 TR16

TR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)

TR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)

TR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)

TR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)

TR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)

TR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)

TR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)

TR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)

TR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)

TR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)

TR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)

TR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)

TR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)

TR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)

TR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)

TR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)

TR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)


EXTICR1

EXTI external interrupt selection register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)


EXTICR2

EXTI external interrupt selection register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)


EXTICR3

EXTI external interrupt selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)


EXTICR4

EXTI external interrupt selection register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)


SWIER1

EXTI software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWIER1 SWIER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWIER0 SWIER1 SWIER2 SWIER3 SWIER4 SWIER5 SWIER6 SWIER7 SWIER8 SWIER9 SWIER10 SWIER11 SWIER12 SWIER13 SWIER14 SWIER15 SWIER16

SWIER0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)

SWIER1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)

SWIER2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)

SWIER3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)

SWIER4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)

SWIER5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)

SWIER6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)

SWIER7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)

SWIER8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)

SWIER9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)

SWIER10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)

SWIER11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)

SWIER12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)

SWIER13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)

SWIER14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)

SWIER15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)

SWIER16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)


IMR1

EXTI CPU wakeup with interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15 IM16 IM19 IM20 IM21 IM22 IM23 IM24 IM25 IM26 IM28 IM29 IM30 IM31

IM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)

IM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)

IM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)

IM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)

IM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)

IM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)

IM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)

IM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)

IM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)

IM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)

IM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)

IM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)

IM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)

IM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)

IM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)

IM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)

IM16 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)

IM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)

IM20 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)

IM21 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)

IM22 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)

IM23 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)

IM24 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)

IM25 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)

IM26 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)

IM28 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)

IM29 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)

IM30 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)

IM31 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)


EMR1

EXTI CPU wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMR1 EMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EM4 EM5 EM6 EM7 EM8 EM9 EM10 EM11 EM12 EM13 EM14 EM15 EM16 EM19 EM21 EM23 EM25 EM26 EM28 EM29 EM30 EM31

EM0 : CPU wakeup with event mask on event input
bits : 0 - 0 (1 bit)

EM1 : CPU wakeup with event mask on event input
bits : 1 - 1 (1 bit)

EM2 : CPU wakeup with event mask on event input
bits : 2 - 2 (1 bit)

EM3 : CPU wakeup with event mask on event input
bits : 3 - 3 (1 bit)

EM4 : CPU wakeup with event mask on event input
bits : 4 - 4 (1 bit)

EM5 : CPU wakeup with event mask on event input
bits : 5 - 5 (1 bit)

EM6 : CPU wakeup with event mask on event input
bits : 6 - 6 (1 bit)

EM7 : CPU wakeup with event mask on event input
bits : 7 - 7 (1 bit)

EM8 : CPU wakeup with event mask on event input
bits : 8 - 8 (1 bit)

EM9 : CPU wakeup with event mask on event input
bits : 9 - 9 (1 bit)

EM10 : CPU wakeup with event mask on event input
bits : 10 - 10 (1 bit)

EM11 : CPU wakeup with event mask on event input
bits : 11 - 11 (1 bit)

EM12 : CPU wakeup with event mask on event input
bits : 12 - 12 (1 bit)

EM13 : CPU wakeup with event mask on event input
bits : 13 - 13 (1 bit)

EM14 : CPU wakeup with event mask on event input
bits : 14 - 14 (1 bit)

EM15 : CPU wakeup with event mask on event input
bits : 15 - 15 (1 bit)

EM16 : CPU wakeup with event mask on event input
bits : 16 - 16 (1 bit)

EM19 : CPU wakeup with event mask on event input
bits : 19 - 19 (1 bit)

EM21 : CPU wakeup with event mask on event input
bits : 21 - 21 (1 bit)

EM23 : CPU wakeup with event mask on event input
bits : 23 - 23 (1 bit)

EM25 : CPU wakeup with event mask on event input
bits : 25 - 25 (1 bit)

EM26 : CPU wakeup with event mask on event input
bits : 26 - 26 (1 bit)

EM28 : CPU wakeup with event mask on event input
bits : 28 - 28 (1 bit)

EM29 : CPU wakeup with event mask on event input
bits : 29 - 29 (1 bit)

EM30 : CPU wakeup with event mask on event input
bits : 30 - 30 (1 bit)

EM31 : CPU wakeup with event mask on event input
bits : 31 - 31 (1 bit)


RPR1

EXTI rising edge pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR1 RPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPIF0 RPIF1 RPIF2 RPIF3 RPIF4 RPIF5 RPIF6 RPIF7 RPIF8 RPIF9 RPIF10 RPIF11 RPIF12 RPIF13 RPIF14 RPIF15 RPIF16

RPIF0 : configurable event inputs x rising edge Pending bit.
bits : 0 - 0 (1 bit)

RPIF1 : configurable event inputs x rising edge Pending bit.
bits : 1 - 1 (1 bit)

RPIF2 : configurable event inputs x rising edge Pending bit.
bits : 2 - 2 (1 bit)

RPIF3 : configurable event inputs x rising edge Pending bit.
bits : 3 - 3 (1 bit)

RPIF4 : configurable event inputs x rising edge Pending bit.
bits : 4 - 4 (1 bit)

RPIF5 : configurable event inputs x rising edge Pending bit
bits : 5 - 5 (1 bit)

RPIF6 : configurable event inputs x rising edge Pending bit.
bits : 6 - 6 (1 bit)

RPIF7 : configurable event inputs x rising edge Pending bit.
bits : 7 - 7 (1 bit)

RPIF8 : configurable event inputs x rising edge Pending bit.
bits : 8 - 8 (1 bit)

RPIF9 : configurable event inputs x rising edge Pending bit.
bits : 9 - 9 (1 bit)

RPIF10 : configurable event inputs x rising edge Pending bit.
bits : 10 - 10 (1 bit)

RPIF11 : configurable event inputs x rising edge Pending bit.
bits : 11 - 11 (1 bit)

RPIF12 : configurable event inputs x rising edge Pending bit.
bits : 12 - 12 (1 bit)

RPIF13 : configurable event inputs x rising edge Pending bit.
bits : 13 - 13 (1 bit)

RPIF14 : configurable event inputs x rising edge Pending bit.
bits : 14 - 14 (1 bit)

RPIF15 : configurable event inputs x rising edge Pending bit.
bits : 15 - 15 (1 bit)

RPIF16 : configurable event inputs x rising edge Pending bit.
bits : 16 - 16 (1 bit)



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