\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATENCY : Latency
bits : 0 - 2 (3 bit)
PRFTEN : Prefetch enable
bits : 8 - 8 (1 bit)
ICEN : Instruction cache enable
bits : 9 - 9 (1 bit)
ICRST : Instruction cache reset
bits : 11 - 11 (1 bit)
EMPTY : Flash User area empty
bits : 16 - 16 (1 bit)
DBG_SWEN : Debug access software enable
bits : 18 - 18 (1 bit)
Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOP : End of operation
bits : 0 - 0 (1 bit)
OPERR : Operation error
bits : 1 - 1 (1 bit)
PROGERR : Programming error
bits : 3 - 3 (1 bit)
WRPERR : Write protected error
bits : 4 - 4 (1 bit)
PGAERR : Programming alignment error
bits : 5 - 5 (1 bit)
SIZERR : Size error
bits : 6 - 6 (1 bit)
PGSERR : Programming sequence error
bits : 7 - 7 (1 bit)
MISERR : Fast programming data miss error
bits : 8 - 8 (1 bit)
FASTERR : Fast programming error
bits : 9 - 9 (1 bit)
RDERR : PCROP read error
bits : 14 - 14 (1 bit)
OPTVERR : Option and Engineering bits loading validity error
bits : 15 - 15 (1 bit)
BSY : Busy
bits : 16 - 16 (1 bit)
CFGBSY : Programming or erase configuration busy.
bits : 18 - 18 (1 bit)
Flash control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG : Programming
bits : 0 - 0 (1 bit)
PER : Page erase
bits : 1 - 1 (1 bit)
MER : Mass erase
bits : 2 - 2 (1 bit)
PNB : Page number
bits : 3 - 8 (6 bit)
STRT : Start
bits : 16 - 16 (1 bit)
OPTSTRT : Options modification start
bits : 17 - 17 (1 bit)
FSTPG : Fast programming
bits : 18 - 18 (1 bit)
EOPIE : End of operation interrupt enable
bits : 24 - 24 (1 bit)
ERRIE : Error interrupt enable
bits : 25 - 25 (1 bit)
RDERRIE : PCROP read error interrupt enable
bits : 26 - 26 (1 bit)
OBL_LAUNCH : Force the option byte loading
bits : 27 - 27 (1 bit)
SEC_PROT : Securable memory area protection enable
bits : 28 - 28 (1 bit)
OPTLOCK : Options Lock
bits : 30 - 30 (1 bit)
LOCK : FLASH_CR Lock
bits : 31 - 31 (1 bit)
Flash ECC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_ECC : ECC fail address
bits : 0 - 13 (14 bit)
access : read-only
SYSF_ECC : ECC fail for Corrected ECC Error or Double ECC Error in info block
bits : 20 - 20 (1 bit)
access : read-only
ECCIE : ECC correction interrupt enable
bits : 24 - 24 (1 bit)
access : read-write
ECCC : ECC correction
bits : 30 - 30 (1 bit)
access : read-write
ECCD : ECC detection
bits : 31 - 31 (1 bit)
access : read-write
Flash option register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDP : Read protection level
bits : 0 - 7 (8 bit)
BOREN : BOR reset Level
bits : 8 - 8 (1 bit)
BORF_LEV : These bits contain the VDD supply level threshold that activates the reset
bits : 9 - 10 (2 bit)
BORR_LEV : These bits contain the VDD supply level threshold that releases the reset.
bits : 11 - 12 (2 bit)
nRST_STOP : nRST_STOP
bits : 13 - 13 (1 bit)
nRST_STDBY : nRST_STDBY
bits : 14 - 14 (1 bit)
nRSTS_HDW : nRSTS_HDW
bits : 15 - 15 (1 bit)
IDWG_SW : Independent watchdog selection
bits : 16 - 16 (1 bit)
IWDG_STOP : Independent watchdog counter freeze in Stop mode
bits : 17 - 17 (1 bit)
IWDG_STDBY : Independent watchdog counter freeze in Standby mode
bits : 18 - 18 (1 bit)
WWDG_SW : Window watchdog selection
bits : 19 - 19 (1 bit)
RAM_PARITY_CHECK : SRAM parity check control
bits : 22 - 22 (1 bit)
nBOOT_SEL : nBOOT_SEL
bits : 24 - 24 (1 bit)
nBOOT1 : Boot configuration
bits : 25 - 25 (1 bit)
nBOOT0 : nBOOT0 option bit
bits : 26 - 26 (1 bit)
NRST_MODE : NRST_MODE
bits : 27 - 28 (2 bit)
IRHEN : Internal reset holder enable bit
bits : 29 - 29 (1 bit)
Flash PCROP zone A Start address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCROP1A_STRT : PCROP1A area start offset
bits : 0 - 7 (8 bit)
Flash PCROP zone A End address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCROP1A_END : PCROP1A area end offset
bits : 0 - 7 (8 bit)
PCROP_RDP : PCROP area preserved when RDP level decreased
bits : 31 - 31 (1 bit)
Flash WRP area A address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRP1A_STRT : WRP area A start offset
bits : 0 - 5 (6 bit)
WRP1A_END : WRP area A end offset
bits : 16 - 21 (6 bit)
Flash WRP area B address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRP1B_STRT : WRP area B start offset
bits : 0 - 5 (6 bit)
WRP1B_END : WRP area B end offset
bits : 16 - 21 (6 bit)
Flash PCROP zone B Start address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCROP1B_STRT : PCROP1B area start offset
bits : 0 - 7 (8 bit)
Flash PCROP zone B End address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCROP1B_END : PCROP1B area end offset
bits : 0 - 7 (8 bit)
Flash key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYR : KEYR
bits : 0 - 31 (32 bit)
Flash Security register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_SIZE : Securable memory area size
bits : 0 - 6 (7 bit)
BOOT_LOCK : used to force boot from user area
bits : 16 - 16 (1 bit)
Option byte key register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OPTKEYR : Option byte key
bits : 0 - 31 (32 bit)
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