\n

SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFGR1

CFGR2

VREFBUF_CSR

VREFBUF_CCR

ITLINE0

ITLINE1

ITLINE2

ITLINE3

ITLINE4

ITLINE5

ITLINE6

ITLINE7

ITLINE8

ITLINE9

ITLINE10

ITLINE11

ITLINE12

ITLINE13

ITLINE14

ITLINE15

ITLINE16

ITLINE17

ITLINE18

ITLINE19

ITLINE20

ITLINE21

ITLINE22

ITLINE23

ITLINE24

ITLINE25

ITLINE26

ITLINE27

ITLINE28

ITLINE29

ITLINE30

ITLINE31


CFGR1

SYSCFG configuration register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE PA11_PA12_RMP IR_POL IR_MOD BOOSTEN UCPD1_STROBE UCPD2_STROBE I2C_PBx_FMP I2C1_FMP I2C2_FMP I2C_PAx_FMP

MEM_MODE : Memory mapping selection bits
bits : 0 - 1 (2 bit)

PA11_PA12_RMP : PA11 and PA12 remapping bit.
bits : 4 - 4 (1 bit)

IR_POL : IR output polarity selection
bits : 5 - 5 (1 bit)

IR_MOD : IR Modulation Envelope signal selection.
bits : 6 - 7 (2 bit)

BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)

UCPD1_STROBE : Strobe signal bit for UCPD1
bits : 9 - 9 (1 bit)

UCPD2_STROBE : Strobe signal bit for UCPD2
bits : 10 - 10 (1 bit)

I2C_PBx_FMP : Fast Mode Plus (FM+) driving capability activation bits
bits : 16 - 19 (4 bit)

I2C1_FMP : FM+ driving capability activation for I2C1
bits : 20 - 20 (1 bit)

I2C2_FMP : FM+ driving capability activation for I2C2
bits : 21 - 21 (1 bit)

I2C_PAx_FMP : Fast Mode Plus (FM+) driving capability activation bits
bits : 22 - 23 (2 bit)


CFGR2

SYSCFG configuration register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKUP_LOCK SRAM_PARITY_LOCK PVD_LOCK ECC_LOCK SRAM_PEF

LOCKUP_LOCK : Cortex-M0+ LOCKUP bit enable bit
bits : 0 - 0 (1 bit)

SRAM_PARITY_LOCK : SRAM parity lock bit
bits : 1 - 1 (1 bit)

PVD_LOCK : PVD lock enable bit
bits : 2 - 2 (1 bit)

ECC_LOCK : ECC error lock bit
bits : 3 - 3 (1 bit)

SRAM_PEF : SRAM parity error flag
bits : 8 - 8 (1 bit)


VREFBUF_CSR

VREFBUF control and status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CSR VREFBUF_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVR HIZ VRR VRS

ENVR : Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
bits : 0 - 0 (1 bit)
access : read-write

HIZ : High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.
bits : 1 - 1 (1 bit)
access : read-write

VRR : Voltage reference buffer ready
bits : 3 - 3 (1 bit)
access : read-only

VRS : Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved
bits : 4 - 6 (3 bit)
access : read-write


VREFBUF_CCR

VREFBUF calibration control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CCR VREFBUF_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.
bits : 0 - 5 (6 bit)


ITLINE0

interrupt line 0 status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE0 ITLINE0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDG

WWDG : Window watchdog interrupt pending flag
bits : 0 - 0 (1 bit)


ITLINE1

interrupt line 1 status register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE1 ITLINE1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVDOUT

PVDOUT : PVD supply monitoring interrupt request pending (EXTI line 16).
bits : 0 - 0 (1 bit)


ITLINE2

interrupt line 2 status register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE2 ITLINE2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP RTC

TAMP : TAMP
bits : 0 - 0 (1 bit)

RTC : RTC
bits : 1 - 1 (1 bit)


ITLINE3

interrupt line 3 status register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE3 ITLINE3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ITF FLASH_ECC

FLASH_ITF : FLASH_ITF
bits : 0 - 0 (1 bit)

FLASH_ECC : FLASH_ECC
bits : 1 - 1 (1 bit)


ITLINE4

interrupt line 4 status register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE4 ITLINE4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCC

RCC : RCC
bits : 0 - 0 (1 bit)


ITLINE5

interrupt line 5 status register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE5 ITLINE5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1

EXTI0 : EXTI0
bits : 0 - 0 (1 bit)

EXTI1 : EXTI1
bits : 1 - 1 (1 bit)


ITLINE6

interrupt line 6 status register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE6 ITLINE6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI2 EXTI3

EXTI2 : EXTI2
bits : 0 - 0 (1 bit)

EXTI3 : EXTI3
bits : 1 - 1 (1 bit)


ITLINE7

interrupt line 7 status register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE7 ITLINE7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7 EXTI8 EXTI9 EXTI10 EXTI11 EXTI12 EXTI13 EXTI14 EXTI15

EXTI4 : EXTI4
bits : 0 - 0 (1 bit)

EXTI5 : EXTI5
bits : 1 - 1 (1 bit)

EXTI6 : EXTI6
bits : 2 - 2 (1 bit)

EXTI7 : EXTI7
bits : 3 - 3 (1 bit)

EXTI8 : EXTI8
bits : 4 - 4 (1 bit)

EXTI9 : EXTI9
bits : 5 - 5 (1 bit)

EXTI10 : EXTI10
bits : 6 - 6 (1 bit)

EXTI11 : EXTI11
bits : 7 - 7 (1 bit)

EXTI12 : EXTI12
bits : 8 - 8 (1 bit)

EXTI13 : EXTI13
bits : 9 - 9 (1 bit)

EXTI14 : EXTI14
bits : 10 - 10 (1 bit)

EXTI15 : EXTI15
bits : 11 - 11 (1 bit)


ITLINE8

interrupt line 8 status register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE8 ITLINE8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCPD1 UCPD2

UCPD1 : UCPD1
bits : 0 - 0 (1 bit)

UCPD2 : UCPD2
bits : 1 - 1 (1 bit)


ITLINE9

interrupt line 9 status register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE9 ITLINE9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1_CH1

DMA1_CH1 : DMA1_CH1
bits : 0 - 0 (1 bit)


ITLINE10

interrupt line 10 status register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE10 ITLINE10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1_CH2 DMA1_CH3

DMA1_CH2 : DMA1_CH1
bits : 0 - 0 (1 bit)

DMA1_CH3 : DMA1_CH3
bits : 1 - 1 (1 bit)


ITLINE11

interrupt line 11 status register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE11 ITLINE11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX DMA1_CH4 DMA1_CH5 DMA1_CH6 DMA1_CH7

DMAMUX : DMAMUX
bits : 0 - 0 (1 bit)

DMA1_CH4 : DMA1_CH4
bits : 1 - 1 (1 bit)

DMA1_CH5 : DMA1_CH5
bits : 2 - 2 (1 bit)

DMA1_CH6 : DMA1_CH6
bits : 3 - 3 (1 bit)

DMA1_CH7 : DMA1_CH7
bits : 4 - 4 (1 bit)


ITLINE12

interrupt line 12 status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE12 ITLINE12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC COMP1 COMP2

ADC : ADC
bits : 0 - 0 (1 bit)

COMP1 : COMP1
bits : 1 - 1 (1 bit)

COMP2 : COMP2
bits : 2 - 2 (1 bit)


ITLINE13

interrupt line 13 status register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE13 ITLINE13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1_CCU TIM1_TRG TIM1_UPD TIM1_BRK

TIM1_CCU : TIM1_CCU
bits : 0 - 0 (1 bit)

TIM1_TRG : TIM1_TRG
bits : 1 - 1 (1 bit)

TIM1_UPD : TIM1_UPD
bits : 2 - 2 (1 bit)

TIM1_BRK : TIM1_BRK
bits : 3 - 3 (1 bit)


ITLINE14

interrupt line 14 status register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE14 ITLINE14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1_CC

TIM1_CC : TIM1_CC
bits : 0 - 0 (1 bit)


ITLINE15

interrupt line 15 status register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE15 ITLINE15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2

TIM2 : TIM2
bits : 0 - 0 (1 bit)


ITLINE16

interrupt line 16 status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE16 ITLINE16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM3

TIM3 : TIM3
bits : 0 - 0 (1 bit)


ITLINE17

interrupt line 17 status register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE17 ITLINE17 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM6 DAC LPTIM1

TIM6 : TIM6
bits : 0 - 0 (1 bit)

DAC : DAC
bits : 1 - 1 (1 bit)

LPTIM1 : LPTIM1
bits : 2 - 2 (1 bit)


ITLINE18

interrupt line 18 status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE18 ITLINE18 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM7 LPTIM2

TIM7 : TIM7
bits : 0 - 0 (1 bit)

LPTIM2 : LPTIM2
bits : 1 - 1 (1 bit)


ITLINE19

interrupt line 19 status register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE19 ITLINE19 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM14

TIM14 : TIM14
bits : 0 - 0 (1 bit)


ITLINE20

interrupt line 20 status register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE20 ITLINE20 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM15

TIM15 : TIM15
bits : 0 - 0 (1 bit)


ITLINE21

interrupt line 21 status register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE21 ITLINE21 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM16

TIM16 : TIM16
bits : 0 - 0 (1 bit)


ITLINE22

interrupt line 22 status register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE22 ITLINE22 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM17

TIM17 : TIM17
bits : 0 - 0 (1 bit)


ITLINE23

interrupt line 23 status register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE23 ITLINE23 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C1

I2C1 : I2C1
bits : 0 - 0 (1 bit)


ITLINE24

interrupt line 24 status register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE24 ITLINE24 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C2

I2C2 : I2C2
bits : 0 - 0 (1 bit)


ITLINE25

interrupt line 25 status register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE25 ITLINE25 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1

SPI1 : SPI1
bits : 0 - 0 (1 bit)


ITLINE26

interrupt line 26 status register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE26 ITLINE26 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI2

SPI2 : SPI2
bits : 0 - 0 (1 bit)


ITLINE27

interrupt line 27 status register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE27 ITLINE27 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1

USART1 : USART1
bits : 0 - 0 (1 bit)


ITLINE28

interrupt line 28 status register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE28 ITLINE28 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART2

USART2 : USART2
bits : 0 - 0 (1 bit)


ITLINE29

interrupt line 29 status register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE29 ITLINE29 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART3 USART4 USART5

USART3 : USART3
bits : 0 - 0 (1 bit)

USART4 : USART4
bits : 1 - 1 (1 bit)

USART5 : USART5
bits : 2 - 2 (1 bit)


ITLINE30

interrupt line 30 status register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE30 ITLINE30 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART2

USART2 : CEC
bits : 0 - 0 (1 bit)


ITLINE31

interrupt line 31 status register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITLINE31 ITLINE31 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNG AES

RNG : RNG
bits : 0 - 0 (1 bit)

AES : AES
bits : 1 - 1 (1 bit)



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