\n

SystemControl

Peripheral Memory Blocks

address_offset : 0x8 Bytes (0x0)
size : 0xD2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCB_ACTLR

SCB_CPUID

SCB_ICSR

SCB_VTOR

SCB_AIRCR

SCB_SCR

SCB_CCR

SCB_SHPR2

SCB_SHPR3

SCB_SHCSR

SCB_DFSR


SCB_ACTLR

Auxiliary Control Register,
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCB_ACTLR SCB_ACTLR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCB_CPUID

CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCB_CPUID SCB_CPUID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REVISION PARTNO VARIANT IMPLEMENTER

REVISION : Indicates patch release: 0x0 = Patch 0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Indicates part number
bits : 4 - 15 (12 bit)
access : read-only

VARIANT : Indicates processor revision: 0x2 = Revision 2
bits : 20 - 23 (4 bit)
access : read-only

IMPLEMENTER : Implementer code
bits : 24 - 31 (8 bit)
access : read-only


SCB_ICSR

Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_ICSR SCB_ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTACTIVE VECTPENDING ISRPENDING PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET NMIPENDSET

VECTACTIVE : Active exception number
bits : 0 - 5 (6 bit)
access : read-only

VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 17 (6 bit)
access : read-only

ISRPENDING : no description available
bits : 22 - 22 (1 bit)
access : read-only

PENDSTCLR : no description available
bits : 25 - 25 (1 bit)
access : write-only

Enumeration:

#0 : 0

no effect

#1 : 1

removes the pending state from the SysTick exception

End of enumeration elements list.

PENDSTSET : no description available
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: SysTick exception is not pending

#1 : 1

write: changes SysTick exception state to pending; read: SysTick exception is pending

End of enumeration elements list.

PENDSVCLR : no description available
bits : 27 - 27 (1 bit)
access : write-only

Enumeration:

#0 : 0

no effect

#1 : 1

removes the pending state from the PendSV exception

End of enumeration elements list.

PENDSVSET : no description available
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PendSV exception is not pending

#1 : 1

write: changes PendSV exception state to pending; read: PendSV exception is pending

End of enumeration elements list.

NMIPENDSET : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: NMI exception is not pending

#1 : 1

write: changes NMI exception state to pending; read: NMI exception is pending

End of enumeration elements list.


SCB_VTOR

Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_VTOR SCB_VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLOFF

TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)
access : read-write


SCB_AIRCR

Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_AIRCR SCB_AIRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTCLRACTIVE SYSRESETREQ ENDIANNESS VECTKEY

VECTCLRACTIVE : no description available
bits : 1 - 1 (1 bit)
access : write-only

SYSRESETREQ : no description available
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

#0 : 0

no system reset request

#1 : 1

asserts a signal to the outer system that requests a reset

End of enumeration elements list.

ENDIANNESS : no description available
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Little-endian

#1 : 1

Big-endian

End of enumeration elements list.

VECTKEY : Register key
bits : 16 - 31 (16 bit)
access : read-write


SCB_SCR

System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_SCR SCB_SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP SEVONPEND

SLEEPONEXIT : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

o not sleep when returning to Thread mode

#1 : 1

enter sleep, or deep sleep, on return from an ISR

End of enumeration elements list.

SLEEPDEEP : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

sleep

#1 : 1

deep sleep

End of enumeration elements list.

SEVONPEND : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded

#1 : 1

enabled events and all interrupts, including disabled interrupts, can wakeup the processor

End of enumeration elements list.


SCB_CCR

Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCB_CCR SCB_CCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNALIGN_TRP STKALIGN

UNALIGN_TRP : Always reads as one, indicates that all unaligned accesses generate a HardFault
bits : 3 - 3 (1 bit)
access : read-only

STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)
access : read-only


SCB_SHPR2

System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_SHPR2 SCB_SHPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_11

PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)
access : read-write


SCB_SHPR3

System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_SHPR3 SCB_SHPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_14 PRI_15

PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)
access : read-write

PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)
access : read-write


SCB_SHCSR

System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_SHCSR SCB_SHCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SVCALLPENDED

SVCALLPENDED : no description available
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

exception is not pending

#1 : 1

exception is pending

End of enumeration elements list.


SCB_DFSR

Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCB_DFSR SCB_DFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALTED BKPT DWTTRAP VCATCH EXTERNAL

HALTED : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No active halt request debug event

#1 : 1

Halt request debug event active

End of enumeration elements list.

BKPT : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No current breakpoint debug event

#1 : 1

At least one current breakpoint debug event

End of enumeration elements list.

DWTTRAP : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No current debug events generated by the DWT

#1 : 1

At least one current debug event generated by the DWT

End of enumeration elements list.

VCATCH : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No Vector catch triggered

#1 : 1

Vector catch triggered

End of enumeration elements list.

EXTERNAL : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No EDBGRQ debug event

#1 : 1

EDBGRQ debug event

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.