\n
address_offset : 0x10 Bytes (0x0)
size : 0x94 byte (0x0)
mem_usage : registers
protection : not protected
EXC02 batch read register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMI : External NMIX pin interrupt request
bits : 0 - -1 (0 bit)
access : read-only
HWINT : Hardware watchdog timer interrupt request
bits : 1 - 0 (0 bit)
access : read-only
IRQ00 Batch Read Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCSINT : Anomalous frequency detection by CSV interrupt request
bits : 0 - -1 (0 bit)
access : read-only
IRQ01 Batch Read Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWWDTINT : Software watchdog timer interrupt request
bits : 0 - -1 (0 bit)
access : read-only
IRQ02 Batch Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVDINT : Low voltage detection (LVD) interrupt request
bits : 0 - -1 (0 bit)
access : read-only
IRQ03 Batch Read Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WAVE0INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
WAVE0INT1 : WFG timer 10 interrupt request in MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
WAVE0INT2 : WFG timer 32 interrupt request in MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
WAVE0INT3 : WFG timer 54 interrupt request in MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
IRQ04 Batch Read Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTINT0 : Interrupt request on external interrupt ch.0
bits : 0 - -1 (0 bit)
access : read-only
EXTINT1 : Interrupt request on external interrupt ch.1
bits : 1 - 0 (0 bit)
access : read-only
EXTINT2 : Interrupt request on external interrupt ch.2
bits : 2 - 1 (0 bit)
access : read-only
EXTINT3 : Interrupt request on external interrupt ch.3
bits : 3 - 2 (0 bit)
access : read-only
EXTINT4 : Interrupt request on external interrupt ch.4
bits : 4 - 3 (0 bit)
access : read-only
EXTINT5 : Interrupt request on external interrupt ch.5
bits : 5 - 4 (0 bit)
access : read-only
EXTINT6 : Interrupt request on external interrupt ch.6
bits : 6 - 5 (0 bit)
access : read-only
EXTINT7 : Interrupt request on external interrupt ch.7
bits : 7 - 6 (0 bit)
access : read-only
IRQ05 Batch Read Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTINT8 : Interrupt request on external interrupt ch.8
bits : 0 - -1 (0 bit)
access : read-only
EXTINT9 : Interrupt request on external interrupt ch.9
bits : 1 - 0 (0 bit)
access : read-only
EXTINT10 : Interrupt request on external interrupt ch.10
bits : 2 - 1 (0 bit)
access : read-only
EXTINT11 : Interrupt request on external interrupt ch.11
bits : 3 - 2 (0 bit)
access : read-only
EXTINT12 : Interrupt request on external interrupt ch.12
bits : 4 - 3 (0 bit)
access : read-only
EXTINT13 : Interrupt request on external interrupt ch.13
bits : 5 - 4 (0 bit)
access : read-only
EXTINT14 : Interrupt request on external interrupt ch.14
bits : 6 - 5 (0 bit)
access : read-only
EXTINT15 : Interrupt request on external interrupt ch.15
bits : 7 - 6 (0 bit)
access : read-only
IRQ06 Batch Read Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.0
bits : 0 - -1 (0 bit)
access : read-only
IRQ07 Batch Read Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.0
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.0
bits : 1 - 0 (0 bit)
access : read-only
IRQ08 Batch Read Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.1
bits : 0 - -1 (0 bit)
access : read-only
IRQ9 Batch Read Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.1
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.1
bits : 1 - 0 (0 bit)
access : read-only
IRQ10 Batch Read Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.2
bits : 0 - -1 (0 bit)
access : read-only
IRQ11 Batch Read Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.2
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.2
bits : 1 - 0 (0 bit)
access : read-only
IRQ12 Batch Read Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.3
bits : 0 - -1 (0 bit)
access : read-only
IRQ13 Batch Read Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.3
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.3
bits : 1 - 0 (0 bit)
access : read-only
IRQ14 Batch Read Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.4
bits : 0 - -1 (0 bit)
access : read-only
IRQ15 Batch Read Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.4
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.4
bits : 1 - 0 (0 bit)
access : read-only
IRQ16 Batch Read Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.5
bits : 0 - -1 (0 bit)
access : read-only
IRQ17 Batch Read Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.5
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.5
bits : 1 - 0 (0 bit)
access : read-only
IRQ18 Batch Read Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.6
bits : 0 - -1 (0 bit)
access : read-only
IRQ19 Batch Read Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.6
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.6
bits : 1 - 0 (0 bit)
access : read-only
IRQ20 Batch Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.7
bits : 0 - -1 (0 bit)
access : read-only
IRQ21 Batch Read Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.7
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.7
bits : 1 - 0 (0 bit)
access : read-only
IRQ22 Batch Read Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPGINT0 : Interrupt request on PPG ch.0
bits : 0 - -1 (0 bit)
access : read-only
PPGINT1 : Interrupt request on PPG ch.2
bits : 1 - 0 (0 bit)
access : read-only
PPGINT2 : Interrupt request on PPG ch.4
bits : 2 - 1 (0 bit)
access : read-only
IRQ23 Batch Read Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MOSCINT : Stabilization wait completion interrupt request for main clock oscillation
bits : 0 - -1 (0 bit)
access : read-only
SOSCINT : Stabilization wait completion interrupt request for sub-clock oscillation
bits : 1 - 0 (0 bit)
access : read-only
MPLLINT : Stabilization wait completion interrupt request for main PLL oscillation
bits : 2 - 1 (0 bit)
access : read-only
RTCINT : RTC interrupt request
bits : 5 - 4 (0 bit)
access : read-only
IRQ24 Batch Read Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCINT0 : Priority conversion interrupt request in the corresponding A/D unit 0.
bits : 0 - -1 (0 bit)
access : read-only
ADCINT1 : Scan conversion interrupt request in the corresponding A/D unit 0.
bits : 1 - 0 (0 bit)
access : read-only
ADCINT2 : FIFO overrun interrupt request in the corresponding A/D unit 0.
bits : 2 - 1 (0 bit)
access : read-only
ADCINT3 : Conversion result comparison interrupt request in the corresponding A/D unit 0.
bits : 3 - 2 (0 bit)
access : read-only
IRQ25 Batch Read Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRT0INT0 : Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
FRT0INT1 : Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
FRT0INT2 : Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
FRT0INT3 : Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
FRT0INT4 : Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only
FRT0INT5 : Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only
IRQ26 Batch Read Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICU0INT0 : Interrupt request on the input capture ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
ICU0INT1 : Interrupt request on the input capture ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
ICU0INT2 : Interrupt request on the input capture ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
ICU0INT3 : Interrupt request on the input capture ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
IRQ27 Batch Read Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OCU0INT0 : Interrupt request on the output compare ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
OCU0INT1 : Interrupt request on the output compare ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
OCU0INT2 : Interrupt request on the output compare ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
OCU0INT3 : Interrupt request on the output compare ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
OCU0INT4 : Interrupt request on the output compare ch.4 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only
OCU0INT5 : Interrupt request on the output compare ch.5 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only
IRQ28 Batch Read Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTINT0 : IRQ0 interrupt request on the base timer ch.0
bits : 0 - -1 (0 bit)
access : read-only
BTINT1 : IRQ1 interrupt request on the base timer ch.0
bits : 1 - 0 (0 bit)
access : read-only
BTINT2 : IRQ0 interrupt request on the base timer ch.1
bits : 2 - 1 (0 bit)
access : read-only
BTINT3 : IRQ1 interrupt request on the base timer ch.1
bits : 3 - 2 (0 bit)
access : read-only
BTINT4 : IRQ0 interrupt request on the base timer ch.2
bits : 4 - 3 (0 bit)
access : read-only
BTINT5 : IRQ1 interrupt request on the base timer ch.2
bits : 5 - 4 (0 bit)
access : read-only
BTINT6 : IRQ0 interrupt request on the base timer ch.3
bits : 6 - 5 (0 bit)
access : read-only
BTINT7 : IRQ1 interrupt request on the base timer ch.3
bits : 7 - 6 (0 bit)
access : read-only
BTINT8 : IRQ0 interrupt request on the base timer ch.4
bits : 8 - 7 (0 bit)
access : read-only
BTINT9 : IRQ1 interrupt request on the base timer ch.4
bits : 9 - 8 (0 bit)
access : read-only
BTINT10 : IRQ0 interrupt request on the base timer ch.5
bits : 10 - 9 (0 bit)
access : read-only
BTINT11 : IRQ1 interrupt request on the base timer ch.5
bits : 11 - 10 (0 bit)
access : read-only
BTINT12 : IRQ0 interrupt request on the base timer ch.6
bits : 12 - 11 (0 bit)
access : read-only
BTINT13 : IRQ1 interrupt request on the base timer ch.6
bits : 13 - 12 (0 bit)
access : read-only
BTINT14 : IRQ0 interrupt request on the base timer ch.7
bits : 14 - 13 (0 bit)
access : read-only
BTINT15 : IRQ1 interrupt request on the base timer ch.7
bits : 15 - 14 (0 bit)
access : read-only
IRQ30 Batch Read Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCEC0INT : Interrupt request for HDMI-CEC/Remote Control Reception ch.0
bits : 5 - 4 (0 bit)
access : read-only
IRQ31 Batch Read Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCEC1INT : Interrupt request for HDMI-CEC/Remote Control Reception ch.1
bits : 6 - 5 (0 bit)
access : read-only
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