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HWWDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC00 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WDG_LDR

WDG_RIS

WDG_VLR

WDG_CTL

WDG_ICL

WDG_LCK


WDG_LDR

Hardware Watchdog Timer Load Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDG_LDR WDG_LDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDG_RIS

Hardware Watchdog Timer Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WDG_RIS WDG_RIS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RIS

RIS : Hardware watchdog interrupt status bit
bits : 0 - -1 (0 bit)
access : read-only


WDG_VLR

Hardware Watchdog Timer Value Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WDG_VLR WDG_VLR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDG_CTL

Hardware Watchdog Timer Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDG_CTL WDG_CTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN RESEN

INTEN : Hardware watchdog interrupt and counter enable bit
bits : 0 - -1 (0 bit)
access : read-write

RESEN : Hardware watchdog reset enable bit
bits : 1 - 0 (0 bit)
access : read-write


WDG_ICL

Hardware Watchdog Timer Clear Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDG_ICL WDG_ICL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

WDG_LCK

Hardware Watchdog Timer Lock Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDG_LCK WDG_LCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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