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FSMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1000 Bytes (0x0)
size : 0xFFFFF400 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

BCR1

BCR3

BWTR1

BWTR2

BWTR3

BWTR4

BTR3

BCR4

BTR4

BTR1

BCR2

BTR2


BCR1

SRAM/NOR-Flash chip-select control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR1 BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BCR3

SRAM/NOR-Flash chip-select control register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR3 BCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BWTR1

SRAM/NOR-Flash write timing registers 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR1 BWTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR2

SRAM/NOR-Flash write timing registers 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR2 BWTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR3

SRAM/NOR-Flash write timing registers 3
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR3 BWTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR4

SRAM/NOR-Flash write timing registers 4
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR4 BWTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BTR3

SRAM/NOR-Flash chip-select timing register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR3 BTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BCR4

SRAM/NOR-Flash chip-select control register 4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR4 BCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BTR4

SRAM/NOR-Flash chip-select timing register 4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR4 BTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BTR1

SRAM/NOR-Flash chip-select timing register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR1 BTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BCR2

SRAM/NOR-Flash chip-select control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR2 BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BTR2

SRAM/NOR-Flash chip-select timing register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR2 BTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)



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