\n

CRTRIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCR_PSR

MCR_FTRM

MCR_RLR


MCR_PSR

High-speed CR oscillation Frequency Division Setup Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR_PSR MCR_PSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CSR

CSR : High-speed CR oscillation frequency division ratio setting bits
bits : 0 - 1 (2 bit)
access : read-write


MCR_FTRM

High-speed CR oscillation Frequency Trimming Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR_FTRM MCR_FTRM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRD

TRD : Frequency trimming setup bits
bits : 0 - 8 (9 bit)
access : read-write


MCR_RLR

High-Speed CR Oscillation Register Write-Protect Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR_RLR MCR_RLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRMLCK

TRMLCK : Register write-protect bits
bits : 0 - 30 (31 bit)
access : read-write



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