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MFT_PPG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x204 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x208 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x210 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x214 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x218 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x240 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x244 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x248 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x250 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x254 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x258 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x380 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TTCR0

COMP4

TRG

REVC

COMP6

PPGC1

PPGC0

PPGC3

PPGC2

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

GATEC0

PPGC5

PPGC4

PPGC7

PPGC6

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

GATEC4

IGBTC

COMP0

COMP2


TTCR0

PPG Start Trigger Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTCR0 TTCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STR0 MONI0 CS0 TRG0O TRG2O TRG4O TRG6O

STR0 : 8-bit UP counter operation enable bit for comparison
bits : 8 - 7 (0 bit)
access : read-write

MONI0 : 8-bit UP counter operation state monitor bit for comparison
bits : 9 - 8 (0 bit)
access : read-only

CS0 : 8-bit UP counter clock select bits for comparison
bits : 10 - 10 (1 bit)
access : read-write

TRG0O : PPG0 trigger stop bit
bits : 12 - 11 (0 bit)
access : read-write

TRG2O : PPG2 trigger stop bit
bits : 13 - 12 (0 bit)
access : read-write

TRG4O : PPG4 trigger stop bit
bits : 14 - 13 (0 bit)
access : read-write

TRG6O : PPG6 trigger stop bit
bits : 15 - 14 (0 bit)
access : read-write


COMP4

PPG Compare Register 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP4 COMP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRG

PPG Start Register 0
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRG TRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEN00 PEN01 PEN02 PEN03 PEN04 PEN05 PEN06 PEN07

PEN00 : PPG0 Start Trigger bit
bits : 0 - -1 (0 bit)
access : read-write

PEN01 : PPG1 Start Trigger bit
bits : 1 - 0 (0 bit)
access : read-write

PEN02 : PPG2 Start Trigger bit
bits : 2 - 1 (0 bit)
access : read-write

PEN03 : PPG3 Start Trigger bit
bits : 3 - 2 (0 bit)
access : read-write

PEN04 : PPG4 Start Trigger bit
bits : 4 - 3 (0 bit)
access : read-write

PEN05 : PPG5 Start Trigger bit
bits : 5 - 4 (0 bit)
access : read-write

PEN06 : PPG6 Start Trigger bit
bits : 6 - 5 (0 bit)
access : read-write

PEN07 : PPG7 Start Trigger bit
bits : 7 - 6 (0 bit)
access : read-write


REVC

Output Reverse Register 0
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REVC REVC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV00 REV01 REV02 REV03 REV04 REV05 REV06 REV07

REV00 : PPG0 Output Reverse Enable bit
bits : 0 - -1 (0 bit)
access : read-write

REV01 : PPG1 Output Reverse Enable bit
bits : 1 - 0 (0 bit)
access : read-write

REV02 : PPG2 Output Reverse Enable bit
bits : 2 - 1 (0 bit)
access : read-write

REV03 : PPG3 Output Reverse Enable bit
bits : 3 - 2 (0 bit)
access : read-write

REV04 : PPG4 Output Reverse Enable bit
bits : 4 - 3 (0 bit)
access : read-write

REV05 : PPG5 Output Reverse Enable bit
bits : 5 - 4 (0 bit)
access : read-write

REV06 : PPG6 Output Reverse Enable bit
bits : 6 - 5 (0 bit)
access : read-write

REV07 : PPG7 Output Reverse Enable bit
bits : 7 - 6 (0 bit)
access : read-write


COMP6

PPG Compare Register 6
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP6 COMP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPGC1

PPG Operation Mode Control Register 1
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC1 PPGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPGC0

PPG Operation Mode Control Register 0
address_offset : 0x201 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC0 PPGC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TTRG MD PCS INTM PUF PIE

TTRG : PPG start trigger select bit
bits : 0 - -1 (0 bit)
access : read-write

MD : PPG Operation Mode Set bits
bits : 1 - 1 (1 bit)
access : read-write

PCS : PPG DOWN Counter Operation Clock Select bits
bits : 3 - 3 (1 bit)
access : read-write

INTM : Interrupt Mode Select bit
bits : 5 - 4 (0 bit)
access : read-write

PUF : PPG Counter Underflow bit
bits : 6 - 5 (0 bit)
access : read-write

PIE : PPG Interrupt Enable bit
bits : 7 - 6 (0 bit)
access : read-write


PPGC3

PPG Operation Mode Control Register 3
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC3 PPGC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPGC2

PPG Operation Mode Control Register 2
address_offset : 0x205 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC2 PPGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL0

PPG0 Reload Registers Low
address_offset : 0x208 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL0 PRLL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRLL

PRLL : Reload Registers Low
bits : 0 - 6 (7 bit)
access : read-write


PRLH0

PPG0 Reload Registers High
address_offset : 0x209 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH0 PRLH0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRLH

PRLH : Reload Registers High
bits : 0 - 6 (7 bit)
access : read-write


PRLL1

PPG1 Reload Registers Low
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL1 PRLL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH1

PPG1 Reload Registers High
address_offset : 0x20D Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH1 PRLH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL2

PPG2 Reload Registers Low
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL2 PRLL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH2

PPG2 Reload Registers High
address_offset : 0x211 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH2 PRLH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL3

PPG3 Reload Registers Low
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL3 PRLL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH3

PPG3 Reload Registers High
address_offset : 0x215 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH3 PRLH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GATEC0

PPG Gate Function Control Registers 0
address_offset : 0x218 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GATEC0 GATEC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EDGE0 STRG0 EDGE2 STRG2

EDGE0 : Select Start Effective Level for PPG0
bits : 0 - -1 (0 bit)
access : read-write

STRG0 : Select a trigger for PPG0
bits : 1 - 0 (0 bit)
access : read-write

EDGE2 : Select Start Effective Level for PPG2
bits : 4 - 3 (0 bit)
access : read-write

STRG2 : Select a trigger for PPG2
bits : 5 - 4 (0 bit)
access : read-write


PPGC5

PPG Operation Mode Control Register 5
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC5 PPGC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPGC4

PPG Operation Mode Control Register 4
address_offset : 0x241 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC4 PPGC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPGC7

PPG Operation Mode Control Register 7
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC7 PPGC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPGC6

PPG Operation Mode Control Register 6
address_offset : 0x245 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPGC6 PPGC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL4

PPG4 Reload Registers Low
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL4 PRLL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH4

PPG4 Reload Registers High
address_offset : 0x249 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH4 PRLH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL5

PPG5 Reload Registers Low
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL5 PRLL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH5

PPG5 Reload Registers High
address_offset : 0x24D Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH5 PRLH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL6

PPG6 Reload Registers Low
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL6 PRLL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH6

PPG6 Reload Registers High
address_offset : 0x251 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH6 PRLH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLL7

PPG7 Reload Registers Low
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLL7 PRLL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRLH7

PPG7 Reload Registers High
address_offset : 0x255 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRLH7 PRLH7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GATEC4

PPG Gate Function Control Registers 4
address_offset : 0x258 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GATEC4 GATEC4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EDGE4 STRG4 EDGE6 STRG6

EDGE4 : Select Start Effective Level for PPG4
bits : 0 - -1 (0 bit)
access : read-write

STRG4 : Select a trigger for PPG4
bits : 1 - 0 (0 bit)
access : read-write

EDGE6 : Select Start Effective Level for PPG6
bits : 4 - 3 (0 bit)
access : read-write

STRG6 : Select a trigger for PPG6
bits : 5 - 4 (0 bit)
access : read-write


IGBTC

IGBT Mode Control Register
address_offset : 0x380 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGBTC IGBTC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IGBTMD IGTRGLV IGOSEL IGNFW IGATIH

IGBTMD : IGBT mode selection bit
bits : 0 - -1 (0 bit)
access : read-write

IGTRGLV : Trigger input level selection bit
bits : 1 - 0 (0 bit)
access : read-write

IGOSEL : Output level selection bit
bits : 2 - 2 (1 bit)
access : read-write

IGNFW : Noise filter width selection bit
bits : 4 - 5 (2 bit)
access : read-write

IGATIH : Stop prohibition mode selection in output active bit
bits : 7 - 6 (0 bit)
access : read-write


COMP0

PPG Compare Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP0 COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COMP2

PPG Compare Register 2
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP2 COMP2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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