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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ENIR

NMIRR

NMICL

EIRR

EICL

ELVR


ENIR

Enable Interrupt Request Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENIR ENIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 EN14 EN15

EN0 : Bit0 of ENIR
bits : 0 - -1 (0 bit)
access : read-write

EN1 : Bit1 of ENIR
bits : 1 - 0 (0 bit)
access : read-write

EN2 : Bit2 of ENIR
bits : 2 - 1 (0 bit)
access : read-write

EN3 : Bit3 of ENIR
bits : 3 - 2 (0 bit)
access : read-write

EN4 : Bit4 of ENIR
bits : 4 - 3 (0 bit)
access : read-write

EN5 : Bit5 of ENIR
bits : 5 - 4 (0 bit)
access : read-write

EN6 : Bit6 of ENIR
bits : 6 - 5 (0 bit)
access : read-write

EN7 : Bit7 of ENIR
bits : 7 - 6 (0 bit)
access : read-write

EN8 : Bit8 of ENIR
bits : 8 - 7 (0 bit)
access : read-write

EN14 : Bit14 of ENIR
bits : 14 - 13 (0 bit)
access : read-write

EN15 : Bit15 of ENIR
bits : 15 - 14 (0 bit)
access : read-write


NMIRR

Non Maskable Interrupt Request Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIRR NMIRR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NR

NR : NMI interrupt request detection bit
bits : 0 - -1 (0 bit)
access : read-only


NMICL

Non Maskable Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICL NMICL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NCL

NCL : NMI interrupt cause clear bit
bits : 0 - -1 (0 bit)
access : read-write


EIRR

External Interrupt Request Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EIRR EIRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 ER8 ER14 ER15

ER0 : Bit0 of EIRR
bits : 0 - -1 (0 bit)
access : read-only

ER1 : Bit1 of EIRR
bits : 1 - 0 (0 bit)
access : read-only

ER2 : Bit2 of EIRR
bits : 2 - 1 (0 bit)
access : read-only

ER3 : Bit3 of EIRR
bits : 3 - 2 (0 bit)
access : read-only

ER4 : Bit4 of EIRR
bits : 4 - 3 (0 bit)
access : read-only

ER5 : Bit5 of EIRR
bits : 5 - 4 (0 bit)
access : read-only

ER6 : Bit6 of EIRR
bits : 6 - 5 (0 bit)
access : read-only

ER7 : Bit7 of EIRR
bits : 7 - 6 (0 bit)
access : read-only

ER8 : Bit8 of EIRR
bits : 8 - 7 (0 bit)
access : read-only

ER14 : Bit14 of EIRR
bits : 14 - 13 (0 bit)
access : read-only

ER15 : Bit15 of EIRR
bits : 15 - 14 (0 bit)
access : read-only


EICL

External Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EICL EICL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECL0 ECL1 ECL2 ECL3 ECL4 ECL5 ECL6 ECL7 ECL8 ECL14 ECL15

ECL0 : Bit0 of EICL
bits : 0 - -1 (0 bit)
access : read-write

ECL1 : Bit1 of EICL
bits : 1 - 0 (0 bit)
access : read-write

ECL2 : Bit2 of EICL
bits : 2 - 1 (0 bit)
access : read-write

ECL3 : Bit3 of EICL
bits : 3 - 2 (0 bit)
access : read-write

ECL4 : Bit4 of EICL
bits : 4 - 3 (0 bit)
access : read-write

ECL5 : Bit5 of EICL
bits : 5 - 4 (0 bit)
access : read-write

ECL6 : Bit6 of EICL
bits : 6 - 5 (0 bit)
access : read-write

ECL7 : Bit7 of EICL
bits : 7 - 6 (0 bit)
access : read-write

ECL8 : Bit8 of EICL
bits : 8 - 7 (0 bit)
access : read-write

ECL14 : Bit14 of EICL
bits : 14 - 13 (0 bit)
access : read-write

ECL15 : Bit15 of EICL
bits : 15 - 14 (0 bit)
access : read-write


ELVR

External Interrupt Level Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ELVR ELVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LA0 LB0 LA1 LB1 LA2 LB2 LA3 LB3 LA4 LB4 LA5 LB5 LA6 LB6 LA7 LB7 LA8 LB8 LA14 LB14 LA15 LB15

LA0 : Bit0 of ELVR
bits : 0 - -1 (0 bit)
access : read-write

LB0 : Bit1 of ELVR
bits : 1 - 0 (0 bit)
access : read-write

LA1 : Bit2 of ELVR
bits : 2 - 1 (0 bit)
access : read-write

LB1 : Bit3 of ELVR
bits : 3 - 2 (0 bit)
access : read-write

LA2 : Bit4 of ELVR
bits : 4 - 3 (0 bit)
access : read-write

LB2 : Bit5 of ELVR
bits : 5 - 4 (0 bit)
access : read-write

LA3 : Bit6 of ELVR
bits : 6 - 5 (0 bit)
access : read-write

LB3 : Bit7 of ELVR
bits : 7 - 6 (0 bit)
access : read-write

LA4 : Bit8 of ELVR
bits : 8 - 7 (0 bit)
access : read-write

LB4 : Bit9 of ELVR
bits : 9 - 8 (0 bit)
access : read-write

LA5 : Bit10 of ELVR
bits : 10 - 9 (0 bit)
access : read-write

LB5 : Bit11 of ELVR
bits : 11 - 10 (0 bit)
access : read-write

LA6 : Bit12 of ELVR
bits : 12 - 11 (0 bit)
access : read-write

LB6 : Bit13 of ELVR
bits : 13 - 12 (0 bit)
access : read-write

LA7 : Bit14 of ELVR
bits : 14 - 13 (0 bit)
access : read-write

LB7 : Bit15 of ELVR
bits : 15 - 14 (0 bit)
access : read-write

LA8 : Bit16 of ELVR
bits : 16 - 15 (0 bit)
access : read-write

LB8 : Bit17 of ELVR
bits : 17 - 16 (0 bit)
access : read-write

LA14 : Bit28 of ELVR
bits : 28 - 27 (0 bit)
access : read-write

LB14 : Bit29 of ELVR
bits : 29 - 28 (0 bit)
access : read-write

LA15 : Bit30 of ELVR
bits : 30 - 29 (0 bit)
access : read-write

LB15 : Bit31 of ELVR
bits : 31 - 30 (0 bit)
access : read-write



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