\n

MFT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x68 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x6C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x74 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x78 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x7C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x84 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x88 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x94 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x98 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x9C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xAC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xBC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OCU_OCCP0

OCU_OCCP4

OCU_OCCP5

OCU_OCSA10

OCU_OCSB10

OCU_OCSA32

OCU_OCSB32

OCU_OCSA54

OCU_OCSB54

OCU_OCSC

FRT_TCCP0

FRT_TCDT0

FRT_TCSA0

FRT_TCSB0

FRT_TCCP1

FRT_TCDT1

OCU_OCCP1

FRT_TCSA1

FRT_TCSB1

FRT_TCCP2

FRT_TCDT2

FRT_TCSA2

FRT_TCSB2

OCU_OCFS10

OCU_OCFS32

OCU_OCFS54

ICU_ICFS10

ICU_ICFS32

ICU_ICCP0

ICU_ICCP1

ICU_ICCP2

ICU_ICCP3

ICU_ICSA10

ICU_ICSB10

ICU_ICSA32

ICU_ICSB32

OCU_OCCP2

WFG_WFTM10

WFG_WFTM32

WFG_WFTM54

WFG_WFSA10

WFG_WFSA32

WFG_WFSA54

WFG_WFIR

WFG_NZCL

ADCMP_ACCP0

ADCMP_ACCPDN0

ADCMP_ACCP1

ADCMP_ACCPDN1

ADCMP_ACCP2

ADCMP_ACCPDN2

ADCMP_ACSB

ADCMP_ACSA

OCU_OCCP3

ADCMP_ATSA


OCU_OCCP0

OCU ch.0 Compare Value Store Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP0 OCU_OCCP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP4

OCU ch.4 Compare Value Store Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP4 OCU_OCCP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP5

OCU ch.5 Compare Value Store Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP5 OCU_OCCP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSA10

"OCU ch.1,0 Control Register A"
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSA10 OCU_OCSA10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CST0 CST1 BDIS0 BDIS1 IOE0 IOE1 IOP0 IOP1

CST0 : Enables the operation of OCU ch.(0)
bits : 0 - -1 (0 bit)
access : read-write

CST1 : Enables the operation of OCU ch.(1)
bits : 1 - 0 (0 bit)
access : read-write

BDIS0 : Disables the buffer function of the OCCP(0) register
bits : 2 - 1 (0 bit)
access : read-write

BDIS1 : Disables the buffer function of the OCCP(1) register
bits : 3 - 2 (0 bit)
access : read-write

IOE0 : "Generates interrupt, when ""1"" is set to OCSA.IOP0"
bits : 4 - 3 (0 bit)
access : read-write

IOE1 : "Generates interrupt, when ""1"" is set to OCSA.IOP1"
bits : 5 - 4 (0 bit)
access : read-write

IOP0 : Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0).
bits : 6 - 5 (0 bit)
access : read-write

IOP1 : Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1).
bits : 7 - 6 (0 bit)
access : read-write


OCU_OCSB10

"OCU ch.1,0 Control Register B"
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSB10 OCU_OCSB10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OTD0 OTD1 CMOD BTS0 BTS1

OTD0 : Indicates that the RT(0) output pin is in the High-level output state.
bits : 0 - -1 (0 bit)
access : read-write

OTD1 : Indicates that the RT(1) output pin is in the High-level output state.
bits : 1 - 0 (0 bit)
access : read-write

CMOD : selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
bits : 4 - 3 (0 bit)
access : read-write

BTS0 : Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT
bits : 5 - 4 (0 bit)
access : read-write

BTS1 : Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT
bits : 6 - 5 (0 bit)
access : read-write


OCU_OCSA32

"OCU ch.3,2 Control Register A"
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSA32 OCU_OCSA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSB32

"OCU ch.3,2 Control Register B"
address_offset : 0x1D Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSB32 OCU_OCSB32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSA54

"OCU ch.5,4 Control Register A"
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSA54 OCU_OCSA54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSB54

"OCU ch.5,4 Control Register B"
address_offset : 0x21 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSB54 OCU_OCSB54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSC

OCU Control Register C
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSC OCU_OCSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD0 MOD1 MOD2 MOD3 MOD4 MOD5

MOD0 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD
bits : 8 - 7 (0 bit)
access : read-write

MOD1 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD
bits : 9 - 8 (0 bit)
access : read-write

MOD2 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD
bits : 10 - 9 (0 bit)
access : read-write

MOD3 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD
bits : 11 - 10 (0 bit)
access : read-write

MOD4 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD
bits : 12 - 11 (0 bit)
access : read-write

MOD5 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD
bits : 13 - 12 (0 bit)
access : read-write


FRT_TCCP0

FRT-ch.0 Cycle Setting Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCCP0 FRT_TCCP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCDT0

FRT-ch.0 Count Value Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCDT0 FRT_TCDT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSA0

FRT-ch.0 Control Register A
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSA0 FRT_TCSA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK SCLR MODE STOP BFE ICRE ICLR IRQZE IRQZF ECKE

CLK : FRT clock cycle
bits : 0 - 2 (3 bit)
access : read-write

SCLR : FRT operation state initialization request
bits : 4 - 3 (0 bit)
access : write-only

MODE : FRT's count mode
bits : 5 - 4 (0 bit)
access : read-write

STOP : Puts FRT in stopping state
bits : 6 - 5 (0 bit)
access : read-write

BFE : Enables TCCP's buffer function
bits : 7 - 6 (0 bit)
access : read-write

ICRE : "Generates interrupt when ""1"" is set to TCSA.ICLR"
bits : 8 - 7 (0 bit)
access : read-write

ICLR : interrupt flag
bits : 9 - 8 (0 bit)
access : read-write

IRQZE : "Generates interrupt, when ""1"" is set to TCSA.IRQZF"
bits : 13 - 12 (0 bit)
access : read-write

IRQZF : zero interrupt flag
bits : 14 - 13 (0 bit)
access : read-write

ECKE : Uses an external input clock (FRCK) as FRT's count clock
bits : 15 - 14 (0 bit)
access : read-write


FRT_TCSB0

FRT-ch.0 Control Register B
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSB0 FRT_TCSB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0E AD1E AD2E

AD0E : Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT
bits : 0 - -1 (0 bit)
access : read-write

AD1E : Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT
bits : 1 - 0 (0 bit)
access : read-write

AD2E : Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT
bits : 2 - 1 (0 bit)
access : read-write


FRT_TCCP1

FRT-ch.1 Cycle Setting Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCCP1 FRT_TCCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCDT1

FRT-ch.1 Count Value Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCDT1 FRT_TCDT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP1

OCU ch.1 Compare Value Store Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP1 OCU_OCCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSA1

FRT-ch.1 Control Register A
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSA1 FRT_TCSA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSB1

FRT-ch.1 Control Register B
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSB1 FRT_TCSB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCCP2

FRT-ch.2 Cycle Setting Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCCP2 FRT_TCCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCDT2

FRT-ch.2 Count Value Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCDT2 FRT_TCDT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSA2

FRT-ch.2 Control Register A
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSA2 FRT_TCSA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSB2

FRT-ch.2 Control Register B
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSB2 FRT_TCSB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCFS10

"OCU ch.1,0 Connecting FRT Select Register"
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCFS10 OCU_OCFS10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSO0 FSO1

FSO0 : Connects FRT ch.x to OCU ch.0
bits : 0 - 2 (3 bit)
access : read-write

FSO1 : Connects FRT ch.x to OCU ch.1
bits : 4 - 6 (3 bit)
access : read-write


OCU_OCFS32

"OCU ch.3,2 Connecting FRT Select Register"
address_offset : 0x59 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCFS32 OCU_OCFS32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCFS54

"OCU ch.5,4 Connecting FRT Select Register"
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCFS54 OCU_OCFS54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICFS10

"ICU ch.1,0 Connecting FRT Select Register"
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICFS10 ICU_ICFS10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSI0 FSI1

FSI0 : Connects FRT ch.x to ICU ch.(0)
bits : 0 - 2 (3 bit)
access : read-write

FSI1 : Connects FRT ch.x to ICU ch.(1)
bits : 4 - 6 (3 bit)
access : read-write


ICU_ICFS32

"ICU ch.3,2 Connecting FRT Select Register"
address_offset : 0x61 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICFS32 ICU_ICFS32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP0

ICU ch.0 Capture value store register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP0 ICU_ICCP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP1

ICU ch.1 Capture value store register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP1 ICU_ICCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP2

ICU ch.2 Capture value store register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP2 ICU_ICCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP3

ICU ch.3 Capture value store register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP3 ICU_ICCP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICSA10

"ICU ch.1,0 Control Register A"
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSA10 ICU_ICSA10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EG0 EG1 ICE0 ICE1 ICP0 ICP1

EG0 : enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)
bits : 0 - 0 (1 bit)
access : read-write

EG1 : enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)
bits : 2 - 2 (1 bit)
access : read-write

ICE0 : "Generates interrupt, when ""1"" is set to ICSA.ICP0."
bits : 4 - 3 (0 bit)
access : read-write

ICE1 : "Generates interrupt, when ""1"" is set to ICSA.ICP1."
bits : 5 - 4 (0 bit)
access : read-write

ICP0 : Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed
bits : 6 - 5 (0 bit)
access : read-write

ICP1 : Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed
bits : 7 - 6 (0 bit)
access : read-write


ICU_ICSB10

"ICU ch.1,0 Control Register B"
address_offset : 0x79 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSB10 ICU_ICSB10 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IEI0 IEI1

IEI0 : indicates the latest valid edge of ICU-ch.(0)
bits : 0 - -1 (0 bit)
access : read-only

IEI1 : indicates the latest valid edge of ICU-ch.(1)
bits : 1 - 0 (0 bit)
access : read-only


ICU_ICSA32

"ICU ch.3,2 Control Register A"
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSA32 ICU_ICSA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICSB32

"ICU ch.3,2 Control Register B"
address_offset : 0x7D Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSB32 ICU_ICSB32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP2

OCU ch.2 Compare Value Store Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP2 OCU_OCCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTM10

WFG ch.10 Timer Value Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTM10 WFG_WFTM10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTM32

WFG ch.32 Timer Value Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTM32 WFG_WFTM32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTM54

WFG ch.54 Timer Value Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTM54 WFG_WFTM54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFSA10

WFG ch.10 Control Register A
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFSA10 WFG_WFSA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCK TMD GTEN PSEL PGEN DMOD

DCK : clock cycle of the WFG timer
bits : 0 - 1 (2 bit)
access : read-write

TMD : WFG's operation mode
bits : 3 - 4 (2 bit)
access : read-write

GTEN : the CH_GATE signal for each channel of WFG
bits : 6 - 6 (1 bit)
access : read-write

PSEL : the PPG timer unit to be used at each channel of WFG
bits : 8 - 8 (1 bit)
access : read-write

PGEN : specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output
bits : 10 - 10 (1 bit)
access : read-write

DMOD : specifies which polarity will be used to output the non-overlap signal
bits : 12 - 11 (0 bit)
access : read-write


WFG_WFSA32

WFG ch.32 Control Register A
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFSA32 WFG_WFSA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFSA54

WFG ch.54 Control Register A
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFSA54 WFG_WFSA54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFIR

WFG Interrupt Control Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFIR WFG_WFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTIF DTIC TMIF10 TMIC10 TMIE10 TMIS10 TMIF32 TMIC32 TMIE32 TMIS32 TMIF54 TMIC54 TMIE54 TMIS54

DTIF : Indicates that DTIF interrupt has been generated.
bits : 0 - -1 (0 bit)
access : read-only

DTIC : Clears WFIR.DTIF and deasserts the DTIF interrupt signal.
bits : 1 - 0 (0 bit)
access : write-only

TMIF10 : Indicates that WFG10 timer interrupt has been generated.
bits : 4 - 3 (0 bit)
access : read-only

TMIC10 : Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal.
bits : 5 - 4 (0 bit)
access : write-only

TMIE10 : Starts the WFG10 timer
bits : 6 - 5 (0 bit)
access : read-write

TMIS10 : Stops the WFG10 timer
bits : 7 - 6 (0 bit)
access : write-only

TMIF32 : Indicates that WFG32 timer interrupt has been generated.
bits : 8 - 7 (0 bit)
access : read-only

TMIC32 : Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal.
bits : 9 - 8 (0 bit)
access : write-only

TMIE32 : Starts the WFG32 timer
bits : 10 - 9 (0 bit)
access : read-write

TMIS32 : Stops the WFG32 timer
bits : 11 - 10 (0 bit)
access : write-only

TMIF54 : Indicates that WFG54 timer interrupt has been generated.
bits : 12 - 11 (0 bit)
access : read-only

TMIC54 : Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal.
bits : 13 - 12 (0 bit)
access : write-only

TMIE54 : Starts the WFG54 timer
bits : 14 - 13 (0 bit)
access : read-write

TMIS54 : Stops the WFG54 timer
bits : 15 - 14 (0 bit)
access : write-only


WFG_NZCL

NZCL Control Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_NZCL WFG_NZCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTIE NWS SDTI

DTIE : DTIF interrupt enable
bits : 0 - -1 (0 bit)
access : read-write

NWS : noise-canceling width of the noise-canceller for the DTTIX pin
bits : 1 - 2 (2 bit)
access : read-write

SDTI : Forcibly generates DTIF interrupt
bits : 4 - 3 (0 bit)
access : write-only


ADCMP_ACCP0

ADCMP ch.0 Compare Value Store Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACCP0 ADCMP_ACCP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACCPDN0

ADCMP ch.0 Compare Value Store Register
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACCPDN0 ADCMP_ACCPDN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACCP1

ADCMP ch.1 Compare Value Store Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACCP1 ADCMP_ACCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACCPDN1

ADCMP ch.1 Compare Value Store Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACCPDN1 ADCMP_ACCPDN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACCP2

ADCMP ch.2 Compare Value Store Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACCP2 ADCMP_ACCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACCPDN2

ADCMP ch.2 Compare Value Store Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACCPDN2 ADCMP_ACCPDN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSB

ADCMP Control Register B
address_offset : 0xB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSB ADCMP_ACSB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BDIS0 BDIS1 BDIS2 BTS0 BTS1 BTS2

BDIS0 : Disables the buffer function of the ACCP0 and ACCPDN0 registers
bits : 0 - -1 (0 bit)
access : read-write

BDIS1 : Disables the buffer function of the ACCP1 and ACCPDN1 registers
bits : 1 - 0 (0 bit)
access : read-write

BDIS2 : Disables the buffer function of the ACCP2 and ACCPDN2 registers
bits : 2 - 1 (0 bit)
access : read-write

BTS0 : Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT
bits : 4 - 3 (0 bit)
access : read-write

BTS1 : Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT
bits : 5 - 4 (0 bit)
access : read-write

BTS2 : Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT
bits : 6 - 5 (0 bit)
access : read-write


ADCMP_ACSA

ADCMP Control Register A
address_offset : 0xBC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSA ADCMP_ACSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE0 CE1 CE2 SEL0 SEL1 SEL2

CE0 : enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected
bits : 0 - 0 (1 bit)
access : read-write

CE1 : enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected
bits : 2 - 2 (1 bit)
access : read-write

CE2 : enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected
bits : 4 - 4 (1 bit)
access : read-write

SEL0 : which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0
bits : 8 - 8 (1 bit)
access : read-write

SEL1 : which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1
bits : 10 - 10 (1 bit)
access : read-write

SEL2 : which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2
bits : 12 - 12 (1 bit)
access : read-write


OCU_OCCP3

OCU ch.3 Compare Value Store Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP3 OCU_OCCP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ATSA

ADC Start Trigger Select Register
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ATSA ADCMP_ATSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0S AD1S AD2S AD0P AD1P AD2P

AD0S : selects the start signal to be used to start the scan conversion of ADC unit0
bits : 0 - 0 (1 bit)
access : read-write

AD1S : selects the start signal to be used to start the scan conversion of ADC unit1
bits : 2 - 2 (1 bit)
access : read-write

AD2S : selects the start signal to be used to start the scan conversion of ADC unit2
bits : 4 - 4 (1 bit)
access : read-write

AD0P : selects the start signal to be used to start priority conversion of ADC unit0
bits : 8 - 8 (1 bit)
access : read-write

AD1P : selects the start signal to be used to start priority conversion of ADC unit1
bits : 10 - 10 (1 bit)
access : read-write

AD2P : selects the start signal to be used to start priority conversion of ADC unit2
bits : 12 - 12 (1 bit)
access : read-write



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