\n
address_offset : 0x0 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
LCDC Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MS : LCD controller display mode selection bits
bits : 2 - 3 (2 bit)
access : read-write
VSEL : LCD drive power control bit
bits : 5 - 4 (0 bit)
access : read-write
LCDEN : Timer mode operation enable bit
bits : 6 - 5 (0 bit)
access : read-write
LCDC Control Register 2
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDIF : Interrupt request detection bit
bits : 0 - -1 (0 bit)
access : read-write
LCDIEN : Interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
BK : Blank display control bit
bits : 2 - 1 (0 bit)
access : read-write
INV : Reverse display control bit
bits : 3 - 2 (0 bit)
access : read-write
BLS8 : 8 COM mode bias selection bit
bits : 4 - 3 (0 bit)
access : read-write
RSEL : Divider resistor value selection bit
bits : 5 - 4 (0 bit)
access : read-write
LCDC SEG Output Enable Register 2
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG32 : Segment 32
bits : 0 - -1 (0 bit)
access : read-write
SEG33 : Segment 33
bits : 1 - 0 (0 bit)
access : read-write
SEG34 : Segment 34
bits : 2 - 1 (0 bit)
access : read-write
SEG35 : Segment 35
bits : 3 - 2 (0 bit)
access : read-write
SEG36 : Segment 36
bits : 4 - 3 (0 bit)
access : read-write
SEG37 : Segment 37
bits : 5 - 4 (0 bit)
access : read-write
SEG38 : Segment 38
bits : 6 - 5 (0 bit)
access : read-write
SEG39 : Segment 39
bits : 7 - 6 (0 bit)
access : read-write
LCDC Blink Setting Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLD00 : Blink operation control bit 0
bits : 0 - -1 (0 bit)
access : read-write
BLD01 : Blink operation control bit 1
bits : 1 - 0 (0 bit)
access : read-write
BLD02 : Blink operation control bit 2
bits : 2 - 1 (0 bit)
access : read-write
BLD03 : Blink operation control bit 3
bits : 3 - 2 (0 bit)
access : read-write
BLD04 : Blink operation control bit 4
bits : 4 - 3 (0 bit)
access : read-write
BLD05 : Blink operation control bit 5
bits : 5 - 4 (0 bit)
access : read-write
BLD06 : Blink operation control bit 6
bits : 6 - 5 (0 bit)
access : read-write
BLD07 : Blink operation control bit 7
bits : 7 - 6 (0 bit)
access : read-write
BLD08 : Blink operation control bit 8
bits : 8 - 7 (0 bit)
access : read-write
BLD09 : Blink operation control bit 9
bits : 9 - 8 (0 bit)
access : read-write
BLD10 : Blink operation control bit 10
bits : 10 - 9 (0 bit)
access : read-write
BLD11 : Blink operation control bit 11
bits : 11 - 10 (0 bit)
access : read-write
BLD12 : Blink operation control bit 12
bits : 12 - 11 (0 bit)
access : read-write
BLD13 : Blink operation control bit 13
bits : 13 - 12 (0 bit)
access : read-write
BLD14 : Blink operation control bit 14
bits : 14 - 13 (0 bit)
access : read-write
BLD15 : Blink operation control bit 15
bits : 15 - 14 (0 bit)
access : read-write
Display Data Memory Register 00
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 00
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 01
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 01
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 02
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 02
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 03
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 03
bits : 0 - 6 (7 bit)
access : read-write
LCDC Control Register 3
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VE0 : VV0 selection bit
bits : 1 - 0 (0 bit)
access : read-write
VE1 : VV1 selection bit
bits : 2 - 1 (0 bit)
access : read-write
VE2 : VV2 selection bit
bits : 3 - 2 (0 bit)
access : read-write
VE3 : VV3 selection bit
bits : 4 - 3 (0 bit)
access : read-write
VE4 : VV4 selection bit
bits : 5 - 4 (0 bit)
access : read-write
BLSEL : Blink interval selection bit
bits : 6 - 5 (0 bit)
access : read-write
PICTL : I/O port input control bit
bits : 7 - 6 (0 bit)
access : read-write
Display Data Memory Register 04
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 04
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 05
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 05
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 06
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 06
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 07
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 07
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 08
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 08
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 09
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 09
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 10
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 10
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 11
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 11
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 12
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 12
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 13
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 13
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 14
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 14
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 15
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 15
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 16
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 16
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 17
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 17
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 18
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 18
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 19
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 19
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 20
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 20
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 21
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 21
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 22
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 22
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 23
address_offset : 0x33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 23
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 24
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 24
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 25
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 25
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 26
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 26
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 27
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 27
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 28
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 28
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 29
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 29
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 30
address_offset : 0x3A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 30
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 31
address_offset : 0x3B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 31
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 32
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 32
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 33
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 33
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 34
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 34
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 35
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 35
bits : 0 - 6 (7 bit)
access : read-write
LCDC Clock Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : LCDC clock division ratio setting bit
bits : 0 - 20 (21 bit)
access : read-write
CLKSEL : Source clock selection bit
bits : 22 - 21 (0 bit)
access : read-write
Display Data Memory Register 36
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 36
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 37
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 37
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 38
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 38
bits : 0 - 6 (7 bit)
access : read-write
Display Data Memory Register 39
address_offset : 0x43 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDRAM : Display Data 39
bits : 0 - 6 (7 bit)
access : read-write
LCDC COM Output Enable Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM0 : Dual purpose COM port control bit
bits : 0 - -1 (0 bit)
access : read-write
COM1 : Dual purpose COM port control bit
bits : 1 - 0 (0 bit)
access : read-write
COM2 : Dual purpose COM port control bit
bits : 2 - 1 (0 bit)
access : read-write
COM3 : Dual purpose COM port control bit
bits : 3 - 2 (0 bit)
access : read-write
COM4 : Dual purpose COM/SEG port control bits
bits : 4 - 3 (0 bit)
access : read-write
COM5 : Dual purpose COM/SEG port control bits
bits : 5 - 4 (0 bit)
access : read-write
COM6 : Dual purpose COM/SEG port control bits
bits : 6 - 5 (0 bit)
access : read-write
COM7 : Dual purpose COM/SEG port control bits
bits : 7 - 6 (0 bit)
access : read-write
LCDC SEG Output Enable Register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG00 : Segment 0
bits : 0 - -1 (0 bit)
access : read-write
SEG01 : Segment 1
bits : 1 - 0 (0 bit)
access : read-write
SEG02 : Segment 2
bits : 2 - 1 (0 bit)
access : read-write
SEG03 : Segment 3
bits : 3 - 2 (0 bit)
access : read-write
SEG04 : Segment 4
bits : 4 - 3 (0 bit)
access : read-write
SEG05 : Segment 5
bits : 5 - 4 (0 bit)
access : read-write
SEG06 : Segment 6
bits : 6 - 5 (0 bit)
access : read-write
SEG07 : Segment 7
bits : 7 - 6 (0 bit)
access : read-write
SEG08 : Segment 8
bits : 8 - 7 (0 bit)
access : read-write
SEG09 : Segment 9
bits : 9 - 8 (0 bit)
access : read-write
SEG10 : Segment 10
bits : 10 - 9 (0 bit)
access : read-write
SEG11 : Segment 11
bits : 11 - 10 (0 bit)
access : read-write
SEG12 : Segment 12
bits : 12 - 11 (0 bit)
access : read-write
SEG13 : Segment 13
bits : 13 - 12 (0 bit)
access : read-write
SEG14 : Segment 14
bits : 14 - 13 (0 bit)
access : read-write
SEG15 : Segment 15
bits : 15 - 14 (0 bit)
access : read-write
SEG16 : Segment 16
bits : 16 - 15 (0 bit)
access : read-write
SEG17 : Segment 17
bits : 17 - 16 (0 bit)
access : read-write
SEG18 : Segment 18
bits : 18 - 17 (0 bit)
access : read-write
SEG19 : Segment 19
bits : 19 - 18 (0 bit)
access : read-write
SEG20 : Segment 20
bits : 20 - 19 (0 bit)
access : read-write
SEG21 : Segment 21
bits : 21 - 20 (0 bit)
access : read-write
SEG22 : Segment 22
bits : 22 - 21 (0 bit)
access : read-write
SEG23 : Segment 23
bits : 23 - 22 (0 bit)
access : read-write
SEG24 : Segment 24
bits : 24 - 23 (0 bit)
access : read-write
SEG25 : Segment 25
bits : 25 - 24 (0 bit)
access : read-write
SEG26 : Segment 26
bits : 26 - 25 (0 bit)
access : read-write
SEG27 : Segment 27
bits : 27 - 26 (0 bit)
access : read-write
SEG28 : Segment 28
bits : 28 - 27 (0 bit)
access : read-write
SEG29 : Segment 29
bits : 29 - 28 (0 bit)
access : read-write
SEG30 : Segment 30
bits : 30 - 29 (0 bit)
access : read-write
SEG31 : Segment 31
bits : 31 - 30 (0 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.