\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
USB Clock Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCEN0 : USB0 clock output enable bit
bits : 0 - -1 (0 bit)
access : read-write
UCSEL : USB clock selection bit
bits : 1 - 0 (0 bit)
access : read-write
UCEN1 : USB1 clock output enable bit
bits : 3 - 2 (0 bit)
access : read-write
USB-PLL Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLN : Frequency division ratio (N) setting bit of the USB-PLL clock
bits : 0 - 5 (6 bit)
access : read-write
USB-PLL Status Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UPRDY : USB-PLL oscillation stabilization bit
bits : 0 - -1 (0 bit)
access : read-only
USB-PLL Interrupt Factor Enable Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPCSE : USB-PLL oscillation stabilization wait complete interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
USB-PLL Interrupt Factor Clear Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPCSC : USB-PLL oscillation stabilization interrupt factor clear bit
bits : 0 - -1 (0 bit)
access : write-only
USB-PLL Interrupt Factor Status Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UPCSI : USB-PLL interrupt factor status bit
bits : 0 - -1 (0 bit)
access : read-only
USB-PLL Control Register 5
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLM : Frequency division ratio (M) setting bit of the USB-PLL clock
bits : 0 - 2 (3 bit)
access : read-write
USB0 Enable Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBEN0 : USB0 enable bit
bits : 0 - -1 (0 bit)
access : read-write
USB1 Enable Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBEN1 : USB1 enable bit
bits : 0 - -1 (0 bit)
access : read-write
USB-PLL Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLEN : USB-PLL oscillation enable bit
bits : 0 - -1 (0 bit)
access : read-write
UPINC : USB-PLL input clock selection bit
bits : 1 - 0 (0 bit)
access : read-write
USB-PLL Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPOWT : USB-PLL oscillation stabilization wait time setting bit
bits : 0 - 1 (2 bit)
access : read-write
USB-PLL Control Register 3
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLK : Frequency division ratio (K) setting bit of the USB-PLL clock
bits : 0 - 3 (4 bit)
access : read-write
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