\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
Entire DMAC Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DH : DMA Halt (All-channel pause bit)
bits : 24 - 26 (3 bit)
access : read-write
PR : Priority Rotation
bits : 28 - 27 (0 bit)
access : read-write
DS : DMA Stop
bits : 30 - 29 (0 bit)
access : read-write
DE : DMA Enable (all-channel operation enable bit)
bits : 31 - 30 (0 bit)
access : read-write
Configuration A Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Transfer Count
bits : 0 - 14 (15 bit)
access : read-write
BC : Block Count
bits : 16 - 18 (3 bit)
access : read-write
IS : Input Select
bits : 23 - 27 (5 bit)
access : read-write
ST : Software Trigger
bits : 29 - 28 (0 bit)
access : read-write
PB : Pause bit (individual-channel pause bit)
bits : 30 - 29 (0 bit)
access : read-write
EB : Enable bit (individual-channel operation enable bit)
bits : 31 - 30 (0 bit)
access : read-write
Configuration B Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM : Enable bit Mask (EB bit clear mask)
bits : 0 - -1 (0 bit)
access : read-write
SS : Stop Status (stop status notification)
bits : 16 - 17 (2 bit)
access : read-write
CI : Completion Interrupt (successful transfer completion interrupt enable)
bits : 19 - 18 (0 bit)
access : read-write
EI : Error Interrupt (unsuccessful transfer completion interrupt enable)
bits : 20 - 19 (0 bit)
access : read-write
RD : Reload Destination
bits : 21 - 20 (0 bit)
access : read-write
RS : Reload Source
bits : 22 - 21 (0 bit)
access : read-write
RC : Reload Count (BC/TC reload)
bits : 23 - 22 (0 bit)
access : read-write
FD : Fixed Destination
bits : 24 - 23 (0 bit)
access : read-write
FS : Fixed Source
bits : 25 - 24 (0 bit)
access : read-write
TW : Transfer Width
bits : 26 - 26 (1 bit)
access : read-write
MS : Mode Select
bits : 28 - 28 (1 bit)
access : read-write
Transfer Source Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 1
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 1
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 2
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 2
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 2
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 3
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 3
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 3
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 4
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 4
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 4
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 5
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 5
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 5
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 6
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 6
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 6
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 6
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration A Register 7
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration B Register 7
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Source Address Register 7
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Destination Address Register 7
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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