\n
address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
QPRC Position Count Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QPRC Maximum Position Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low-Order Bytes of QPRC Interrupt Control Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QPCMIE : PC match interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
QPCMF : PC match interrupt request flag bit
bits : 1 - 0 (0 bit)
access : read-write
QPRCMIE : PC and RC match interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
QPRCMF : PC and RC match interrupt request flag bit
bits : 3 - 2 (0 bit)
access : read-write
OUZIE : Overflow, underflow, or zero index interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write
UFDF : Underflow interrupt request flag bit
bits : 5 - 4 (0 bit)
access : read-write
OFDF : Overflow interrupt request flag bit
bits : 6 - 5 (0 bit)
access : read-write
ZIIF : Zero index interrupt request flag bit
bits : 7 - 6 (0 bit)
access : read-write
High-Order Bytes of QPRC Interrupt Control Register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDCIE : Count inversion interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
CDCF : Count inversion interrupt request flag bit
bits : 1 - 0 (0 bit)
access : read-write
DIRPC : Last position counter direction bit
bits : 2 - 1 (0 bit)
access : read-only
DIROU : Last position counter flow direction bit
bits : 3 - 2 (0 bit)
access : read-only
QPCNRCMIE : PC match and RC match interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write
QPCNRCMF : PC match and RC match interrupt request flag bit
bits : 5 - 4 (0 bit)
access : read-write
QPRC Control Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCM : Position counter mode bits
bits : 0 - 0 (1 bit)
access : read-write
RCM : Revolution counter mode bits
bits : 2 - 2 (1 bit)
access : read-write
PSTP : Position counter stop bit
bits : 4 - 3 (0 bit)
access : read-write
CGSC : Count clear or gate selection bit
bits : 5 - 4 (0 bit)
access : read-write
RSEL : Register function selection bit
bits : 6 - 5 (0 bit)
access : read-write
SWAP : Swap bit
bits : 7 - 6 (0 bit)
access : read-write
PCRM : Position counter reset mask bits
bits : 8 - 8 (1 bit)
access : read-write
AES : AIN detection edge selection bits
bits : 10 - 10 (1 bit)
access : read-write
BES : BIN detection edge selection bits
bits : 12 - 12 (1 bit)
access : read-write
CGE : Detection edge selection bits
bits : 14 - 14 (1 bit)
access : read-write
QPRC Extension Control Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ORNGMD : Outrange mode selection bit
bits : 0 - -1 (0 bit)
access : read-write
ORNGF : Outrange interrupt request flag bit
bits : 1 - 0 (0 bit)
access : read-write
ORNGIE : Outrange interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
Quad Counter Position Rotation Count Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
QPCRR : Quad counter position count display bit
bits : 0 - 14 (15 bit)
access : read-only
QRCRR : Quad counter rotation count display bit
bits : 16 - 30 (15 bit)
access : read-only
QPRC Revolution Count Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QPRC Position Counter Compare Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QPRC Position and Revolution Counter Compare Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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