\n
address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
PWM Cycle Set Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0
LOW Width Reload Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0
PWM Cycle Set Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0
Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0
UDIR : Underflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write
DTIR : Duty match interrupt request bit
bits : 1 - 0 (0 bit)
access : read-write
TGIR : Trigger interrupt request bit
bits : 2 - 1 (0 bit)
access : read-write
UDIE : Underflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write
DTIE : Duty match interrupt request enable bit
bits : 5 - 4 (0 bit)
access : read-write
TGIE : Trigger interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write
Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0
UDIR : Underflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write
TGIR : Trigger interrupt request bit
bits : 2 - 1 (0 bit)
access : read-write
UDIE : Underflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write
TGIE : Trigger interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write
Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0
UDIR : Underflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write
TGIR : Trigger interrupt request bit
bits : 2 - 1 (0 bit)
access : read-write
UDIE : Underflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write
TGIE : Trigger interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write
Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0
OVIR : Overflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write
EDIR : Measurement completion interrupt request bit
bits : 2 - 1 (0 bit)
access : read-only
OVIE : Overflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write
EDIE : Measurement completion interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write
ERR : Error flag bit
bits : 7 - 6 (0 bit)
access : read-only
Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0
CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write
Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0
CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write
Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0
CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write
GATE : Gate Input Enable bit
bits : 7 - 6 (0 bit)
access : read-write
Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0
CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write
PWM Duty Set Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0
HIGH Width Reload Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0
Data Buffer Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0
Timer Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0
Timer Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0
Timer Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0
Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0
STRG : Software trigger bit
bits : 0 - -1 (0 bit)
access : read-write
CTEN : Count operation enable bit
bits : 1 - 0 (0 bit)
access : read-write
MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write
OSEL : Output polarity specification bit
bits : 3 - 2 (0 bit)
access : read-write
FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write
EGS : Trigger input edge selection bits
bits : 8 - 8 (1 bit)
access : read-write
PMSK : Pulse output mask bit
bits : 10 - 9 (0 bit)
access : read-write
RTGEN : Restart enable bit
bits : 11 - 10 (0 bit)
access : read-write
CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write
Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0
STRG : Software trigger bit
bits : 0 - -1 (0 bit)
access : read-write
CTEN : Count operation enable bit
bits : 1 - 0 (0 bit)
access : read-write
MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write
OSEL : Output polarity specification bit
bits : 3 - 2 (0 bit)
access : read-write
FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write
EGS : Trigger input edge selection bits
bits : 8 - 8 (1 bit)
access : read-write
PMSK : Pulse output mask bit
bits : 10 - 9 (0 bit)
access : read-write
RTGEN : Restart enable bit
bits : 11 - 10 (0 bit)
access : read-write
CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write
Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0
STRG : Software trigger bit
bits : 0 - -1 (0 bit)
access : read-write
CTEN : Timer enable bit
bits : 1 - 0 (0 bit)
access : read-write
MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write
OSEL : Output polarity specification bit
bits : 3 - 2 (0 bit)
access : read-write
FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write
T32 : 32-bit timer selection bit
bits : 7 - 6 (0 bit)
access : read-write
EGS : Trigger input edge selection bits
bits : 8 - 8 (1 bit)
access : read-write
CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write
Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0
CTEN : Timer enable bit
bits : 1 - 0 (0 bit)
access : read-write
MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write
FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write
T32 : 32-bit timer selection bit
bits : 7 - 6 (0 bit)
access : read-write
EGS : Measurement edge selection bits
bits : 8 - 9 (2 bit)
access : read-write
CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write
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