\n
address_offset : 0x0 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
Watch Counter Read Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTR : Counter read bits
bits : 0 - 4 (5 bit)
access : read-only
Watch Counter Reload Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RLC : Counter reload value setting bits
bits : 0 - 4 (5 bit)
access : read-write
Clock Selection Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL_IN : Input clock selection bit
bits : 0 - 0 (1 bit)
access : read-write
SEL_OUT : Output clock selection bit
bits : 8 - 9 (2 bit)
access : read-write
Division Clock Enable Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_EN : Division clock enable bit
bits : 0 - -1 (0 bit)
access : read-write
CLK_EN_R : Division clock enable read bit
bits : 1 - 0 (0 bit)
access : read-write
Watch Counter Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCIF : Interrupt request flag bit
bits : 0 - -1 (0 bit)
access : read-write
WCIE : Interrupt request enable bit
bits : 1 - 0 (0 bit)
access : read-write
CS : Count clock select bits
bits : 2 - 2 (1 bit)
access : read-write
WCOP : Watch counter operating state flag
bits : 6 - 5 (0 bit)
access : read-only
WCEN : Watch counter operation enable bit
bits : 7 - 6 (0 bit)
access : read-write
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