\n
address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
Mode Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTH : specify Data Width
bits : 0 - 0 (1 bit)
access : read-write
RBMON : Read Byte Mask ON
bits : 2 - 1 (0 bit)
access : read-write
WEOFF : disable the write enable signal (MWEX) operation
bits : 3 - 2 (0 bit)
access : read-write
NAND : NAND Flash memory mode
bits : 4 - 3 (0 bit)
access : read-write
PAGE : NOR Flash memory page access mode
bits : 5 - 4 (0 bit)
access : read-write
RDY : control the external RDY function
bits : 6 - 5 (0 bit)
access : read-write
SHRTDOUT : select to which idle cycle the write data output is extended
bits : 7 - 6 (0 bit)
access : read-write
Mode Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RACC : Read Access Cycle
bits : 0 - 2 (3 bit)
access : read-write
RADC : Read Address Setup cycle
bits : 4 - 6 (3 bit)
access : read-write
FRADC : First Read Address Cycle
bits : 8 - 10 (3 bit)
access : read-write
RIDLC : Read Idle Cycle
bits : 12 - 14 (3 bit)
access : read-write
WACC : Write Access Cycle
bits : 16 - 18 (3 bit)
access : read-write
WADC : Write Address Setup cycle
bits : 20 - 22 (3 bit)
access : read-write
WWEC : Write Enable Cycle
bits : 24 - 26 (3 bit)
access : read-write
WIDLC : Write Idle Cycle
bits : 28 - 30 (3 bit)
access : read-write
Timing Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 7
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Area Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 7
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Mode Register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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