\n
address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x5C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x68 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x6C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x74 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x78 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x7C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x84 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x88 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x94 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x98 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x9C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xAC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xBC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
OCU ch.0 Compare Value Store Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.4 Compare Value Store Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5 Compare Value Store Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.1,0 Control Register A
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CST0 : Enables the operation of OCU ch.(0)
bits : 0 - -1 (0 bit)
access : read-write
CST1 : Enables the operation of OCU ch.(1)
bits : 1 - 0 (0 bit)
access : read-write
BDIS0 : Disables the buffer function of the OCCP(0) register
bits : 2 - 1 (0 bit)
access : read-write
BDIS1 : Disables the buffer function of the OCCP(1) register
bits : 3 - 2 (0 bit)
access : read-write
IOE0 : Generates interrupt, when 1 is set to OCSA.IOP0
bits : 4 - 3 (0 bit)
access : read-write
IOE1 : Generates interrupt, when 1 is set to OCSA.IOP1
bits : 5 - 4 (0 bit)
access : read-write
IOP0 : Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0).
bits : 6 - 5 (0 bit)
access : read-write
IOP1 : Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1).
bits : 7 - 6 (0 bit)
access : read-write
OCU ch.1,0 Control Register B
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTD0 : Indicates that the RT(0) output pin is in the High-level output state.
bits : 0 - -1 (0 bit)
access : read-write
OTD1 : Indicates that the RT(1) output pin is in the High-level output state.
bits : 1 - 0 (0 bit)
access : read-write
CMOD : selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
bits : 4 - 3 (0 bit)
access : read-write
BTS0 : Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT
bits : 5 - 4 (0 bit)
access : read-write
BTS1 : Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT
bits : 6 - 5 (0 bit)
access : read-write
OCU ch.3,2 Control Register A
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.3,2 Control Register B
address_offset : 0x1D Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5,4 Control Register A
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5,4 Control Register B
address_offset : 0x21 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU Control Register C
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD0 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD
bits : 8 - 7 (0 bit)
access : read-write
MOD1 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD
bits : 9 - 8 (0 bit)
access : read-write
MOD2 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD
bits : 10 - 9 (0 bit)
access : read-write
MOD3 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD
bits : 11 - 10 (0 bit)
access : read-write
MOD4 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD
bits : 12 - 11 (0 bit)
access : read-write
MOD5 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD
bits : 13 - 12 (0 bit)
access : read-write
FRT-ch.0 Cycle Setting Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.0 Count Value Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.0 Control Register A
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK : FRT clock cycle
bits : 0 - 2 (3 bit)
access : read-write
SCLR : FRT operation state initialization request
bits : 4 - 3 (0 bit)
access : write-only
MODE : FRT's count mode
bits : 5 - 4 (0 bit)
access : read-write
STOP : Puts FRT in stopping state
bits : 6 - 5 (0 bit)
access : read-write
BFE : Enables TCCP's buffer function
bits : 7 - 6 (0 bit)
access : read-write
ICRE : Generates interrupt when 1 is set to TCSA.ICLR
bits : 8 - 7 (0 bit)
access : read-write
ICLR : interrupt flag
bits : 9 - 8 (0 bit)
access : read-write
IRQZE : Generates interrupt, when 1 is set to TCSA.IRQZF
bits : 13 - 12 (0 bit)
access : read-write
IRQZF : zero interrupt flag
bits : 14 - 13 (0 bit)
access : read-write
ECKE : Uses an external input clock (FRCK) as FRT's count clock
bits : 15 - 14 (0 bit)
access : read-write
FRT-ch.0 Control Register B
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD0E : Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT
bits : 0 - -1 (0 bit)
access : read-write
AD1E : Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT
bits : 1 - 0 (0 bit)
access : read-write
AD2E : Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT
bits : 2 - 1 (0 bit)
access : read-write
FRT-ch.1 Cycle Setting Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.1 Count Value Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.1 Compare Value Store Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.1 Control Register A
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.1 Control Register B
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Cycle Setting Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Count Value Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Control Register A
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Control Register B
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.1,0 Connecting FRT Select Register
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSO0 : Connects FRT ch.x to OCU ch.0
bits : 0 - 2 (3 bit)
access : read-write
FSO1 : Connects FRT ch.x to OCU ch.1
bits : 4 - 6 (3 bit)
access : read-write
OCU ch.3,2 Connecting FRT Select Register
address_offset : 0x59 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5,4 Connecting FRT Select Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.1,0 Connecting FRT Select Register
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSI0 : Connects FRT ch.x to ICU ch.(0)
bits : 0 - 2 (3 bit)
access : read-write
FSI1 : Connects FRT ch.x to ICU ch.(1)
bits : 4 - 6 (3 bit)
access : read-write
ICU ch.3,2 Connecting FRT Select Register
address_offset : 0x61 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.0 Capture value store register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICU ch.1 Capture value store register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.2 Capture value store register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.3 Capture value store register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.1,0 Control Register A
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EG0 : enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)
bits : 0 - 0 (1 bit)
access : read-write
EG1 : enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)
bits : 2 - 2 (1 bit)
access : read-write
ICE0 : Generates interrupt, when 1 is set to ICSA.ICP0.
bits : 4 - 3 (0 bit)
access : read-write
ICE1 : Generates interrupt, when 1 is set to ICSA.ICP1.
bits : 5 - 4 (0 bit)
access : read-write
ICP0 : Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed
bits : 6 - 5 (0 bit)
access : read-write
ICP1 : Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed
bits : 7 - 6 (0 bit)
access : read-write
ICU ch.1,0 Control Register B
address_offset : 0x79 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IEI0 : indicates the latest valid edge of ICU-ch.(0)
bits : 0 - -1 (0 bit)
access : read-only
IEI1 : indicates the latest valid edge of ICU-ch.(1)
bits : 1 - 0 (0 bit)
access : read-only
ICU ch.3,2 Control Register A
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.3,2 Control Register B
address_offset : 0x7D Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.2 Compare Value Store Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.10 Timer Value Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.32 Timer Value Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.54 Timer Value Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.10 Control Register A
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCK : clock cycle of the WFG timer
bits : 0 - 1 (2 bit)
access : read-write
TMD : WFG's operation mode
bits : 3 - 4 (2 bit)
access : read-write
GTEN : the CH_GATE signal for each channel of WFG
bits : 6 - 6 (1 bit)
access : read-write
PSEL : the PPG timer unit to be used at each channel of WFG
bits : 8 - 8 (1 bit)
access : read-write
PGEN : specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output
bits : 10 - 10 (1 bit)
access : read-write
DMOD : specifies which polarity will be used to output the non-overlap signal
bits : 12 - 11 (0 bit)
access : read-write
WFG ch.32 Control Register A
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.54 Control Register A
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG Interrupt Control Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTIF : Indicates that DTIF interrupt has been generated.
bits : 0 - -1 (0 bit)
access : read-only
DTIC : Clears WFIR.DTIF and deasserts the DTIF interrupt signal.
bits : 1 - 0 (0 bit)
access : write-only
TMIF10 : Indicates that WFG10 timer interrupt has been generated.
bits : 4 - 3 (0 bit)
access : read-only
TMIC10 : Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal.
bits : 5 - 4 (0 bit)
access : write-only
TMIE10 : Starts the WFG10 timer
bits : 6 - 5 (0 bit)
access : read-write
TMIS10 : Stops the WFG10 timer
bits : 7 - 6 (0 bit)
access : write-only
TMIF32 : Indicates that WFG32 timer interrupt has been generated.
bits : 8 - 7 (0 bit)
access : read-only
TMIC32 : Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal.
bits : 9 - 8 (0 bit)
access : write-only
TMIE32 : Starts the WFG32 timer
bits : 10 - 9 (0 bit)
access : read-write
TMIS32 : Stops the WFG32 timer
bits : 11 - 10 (0 bit)
access : write-only
TMIF54 : Indicates that WFG54 timer interrupt has been generated.
bits : 12 - 11 (0 bit)
access : read-only
TMIC54 : Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal.
bits : 13 - 12 (0 bit)
access : write-only
TMIE54 : Starts the WFG54 timer
bits : 14 - 13 (0 bit)
access : read-write
TMIS54 : Stops the WFG54 timer
bits : 15 - 14 (0 bit)
access : write-only
NZCL Control Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTIE : DTIF interrupt enable
bits : 0 - -1 (0 bit)
access : read-write
NWS : noise-canceling width of the noise-canceller for the DTTIX pin
bits : 1 - 2 (2 bit)
access : read-write
SDTI : Forcibly generates DTIF interrupt
bits : 4 - 3 (0 bit)
access : write-only
ADCMP ch.0 Compare Value Store Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP ch.0 Compare Value Store Register
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP ch.1 Compare Value Store Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP ch.1 Compare Value Store Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP ch.2 Compare Value Store Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP ch.2 Compare Value Store Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Control Register B
address_offset : 0xB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BDIS0 : Disables the buffer function of the ACCP0 and ACCPDN0 registers
bits : 0 - -1 (0 bit)
access : read-write
BDIS1 : Disables the buffer function of the ACCP1 and ACCPDN1 registers
bits : 1 - 0 (0 bit)
access : read-write
BDIS2 : Disables the buffer function of the ACCP2 and ACCPDN2 registers
bits : 2 - 1 (0 bit)
access : read-write
BTS0 : Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT
bits : 4 - 3 (0 bit)
access : read-write
BTS1 : Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT
bits : 5 - 4 (0 bit)
access : read-write
BTS2 : Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT
bits : 6 - 5 (0 bit)
access : read-write
ADCMP Control Register A
address_offset : 0xBC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CE0 : enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected
bits : 0 - 0 (1 bit)
access : read-write
CE1 : enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected
bits : 2 - 2 (1 bit)
access : read-write
CE2 : enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected
bits : 4 - 4 (1 bit)
access : read-write
SEL0 : which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0
bits : 8 - 8 (1 bit)
access : read-write
SEL1 : which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1
bits : 10 - 10 (1 bit)
access : read-write
SEL2 : which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2
bits : 12 - 12 (1 bit)
access : read-write
OCU ch.3 Compare Value Store Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Start Trigger Select Register
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD0S : selects the start signal to be used to start the scan conversion of ADC unit0
bits : 0 - 0 (1 bit)
access : read-write
AD1S : selects the start signal to be used to start the scan conversion of ADC unit1
bits : 2 - 2 (1 bit)
access : read-write
AD2S : selects the start signal to be used to start the scan conversion of ADC unit2
bits : 4 - 4 (1 bit)
access : read-write
AD0P : selects the start signal to be used to start priority conversion of ADC unit0
bits : 8 - 8 (1 bit)
access : read-write
AD1P : selects the start signal to be used to start priority conversion of ADC unit1
bits : 10 - 10 (1 bit)
access : read-write
AD2P : selects the start signal to be used to start priority conversion of ADC unit2
bits : 12 - 12 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.