\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x700 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x704 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x708 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x710 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x800 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x714 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
Sub Oscillation Circuit Power Supply Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISUBSEL : Sub oscillation circuit current setting bits
bits : 1 - 1 (1 bit)
access : read-write
Sub Clock Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCCKE : RTC clock control bit
bits : 0 - -1 (0 bit)
access : read-write
RTC Mode Control Register
address_offset : 0x700 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCE : RTC mode control bit
bits : 0 - -1 (0 bit)
access : read-write
Deep Standby Return Cause Register 1
address_offset : 0x704 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINITX : INITX pin input reset return bit
bits : 0 - -1 (0 bit)
access : read-write
WLVDH : Low-voltage detection reset return bit
bits : 1 - 0 (0 bit)
access : read-write
Deep Standby Return Cause Register 2
address_offset : 0x708 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRTCI : RTC interrupt return bit
bits : 0 - -1 (0 bit)
access : read-only
WLVDI : LVD interrupt return bit
bits : 1 - 0 (0 bit)
access : read-only
WUI0 : WKUP pin input return bit 0
bits : 2 - 1 (0 bit)
access : read-only
WUI1 : WKUP pin input return bit 1
bits : 3 - 2 (0 bit)
access : read-only
WUI2 : WKUP pin input return bit 2
bits : 4 - 3 (0 bit)
access : read-only
WUI3 : WKUP pin input return bit 3
bits : 5 - 4 (0 bit)
access : read-only
Deep Standby Return Enable Register
address_offset : 0x70C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRTCE : RTC interrupt return enable bit
bits : 0 - -1 (0 bit)
access : read-write
WLVDE : LVD interrupt return enable bit
bits : 1 - 0 (0 bit)
access : read-write
WUI1E : WKUP pin input return enable bit 1
bits : 3 - 2 (0 bit)
access : read-write
WUI2E : WKUP pin input return enable bit 2
bits : 4 - 3 (0 bit)
access : read-write
WUI3E : WKUP pin input return enable bit 3
bits : 5 - 4 (0 bit)
access : read-write
WKUP Pin Input Level Register
address_offset : 0x710 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUI1LV : WKUP pin input level select bit 1
bits : 0 - -1 (0 bit)
access : read-write
WUI2LV : WKUP pin input level select bit 2
bits : 1 - 0 (0 bit)
access : read-write
WUI3LV : WKUP pin input level select bit 3
bits : 2 - 1 (0 bit)
access : read-write
Deep Standby RAM Retention Register
address_offset : 0x714 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMR : On-chip SRAM retention control bits
bits : 0 - 0 (1 bit)
access : read-write
Backup Registers from 1
address_offset : 0x800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 2
address_offset : 0x801 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 3
address_offset : 0x802 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 4
address_offset : 0x803 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 5
address_offset : 0x804 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 6
address_offset : 0x805 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 7
address_offset : 0x806 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 8
address_offset : 0x807 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 9
address_offset : 0x808 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 10
address_offset : 0x809 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 11
address_offset : 0x80A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 12
address_offset : 0x80B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 13
address_offset : 0x80C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 14
address_offset : 0x80D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 15
address_offset : 0x80E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Backup Registers from 16
address_offset : 0x80F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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